HyGCN: A GCN Accelerator with Hybrid Architecture

Abstract

Inspired by the great success of neural networks, graph convolutional neural networks (GCNs) are proposed to analyze graph data. GCNs mainly include two phases with distinct execution patterns. The Aggregation phase, behaves as graph processing, showing a dynamic and irregular execution pattern. The Combination phase, acts more like the neural networks, presenting a static and regular execution pattern. The hybrid execution patterns of GCNs require a design that alleviates irregularity and exploits regularity. Moreover, to achieve higher performance and energy efficiency, the design needs to leverage the high intra-vertex parallelism in Aggregation phase, the highly reusable inter-vertex data in Combination phase, and the opportunity to fuse phase-by-phase execution introduced by the new features of GCNs. However, existing architectures fail to address these demands.In this work, we first characterize the hybrid execution patterns of GCNs on Intel Xeon CPU. Guided by the characterization, we design a GCN accelerator, HyGCN, using a hybrid architecture to efficiently perform GCNs. Specifically, first, we build a new programming model to exploit the fine-grained parallelism for our hardware design. Second, we propose a hardware design with two efficient processing engines to alleviate the irregularity of Aggregation phase and leverage the regularity of Combination phase. Besides, these engines can exploit various parallelism and reuse highly reusable data efficiently. Third, we optimize the overall system via inter-engine pipeline for inter-phase fusion and priority-based off-chip memory access coordination to improve off-chip bandwidth utilization. Compared to the state-of-the-art software framework running on Intel Xeon CPU and NVIDIA V100 GPU, our work achieves on average 1509× speedup with 2500× energy reduction and average 6.5× speedup with 10× energy reduction, respectively. * Corresponding author is Xiaochun Ye and his email is yexi-aochun@ict.ac.cn.

DeepBurning-GL

“…The increasing deployment of domain-specific accelerator design for neural network [1,18] and graph [4,8] motivates the development of customized GNN accelerators on both FPGAs and ASICs recently. The authors in [26] abstracted the execution flow of GCN into the aggregation stage and the combination stage and then developed an accelerator called HyGCN based on the processing stages. They leveraged both the SIMD and the systolic arrays to deal with the coexistence problem of GNNs.…”

“…Although specialized GNN accelerators of ASICs such as HyGCN [26] and EnGN [7], are tailored as alternatives to CPU and GPU, they are still not flexible enough to meet the requirements of various GNN-based applications from the cloud to edge. First and foremost, because graph learning is a fast-developing field and novel GNN architectures keep emerging, ASIC-based accelerators of fixed architecture sometimes cannot run state-of-the-art GNN models.…”

FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization

“…AWB-GCN [11] implements amount of process elements for multiply-accumulate-cell (MAC) and balance the workload of process elements to accelerate the sparse matrix multiplication. Other works [10,13,14] accelerate GCNs by designing efficient pipeline architecture, optimizing memory mode, and increasing parallelism.…”

“…In contrast, there are two memory synchronizations between the three steps of each layer in GATs because of the masked self-attention mechanism [1]. The basic calculation of the existing works on GCNs and CNNs [10][11][12][13][14][15][16][17][18][19] has no change which still use multiplication with heavy dependence on DSPs. Moreover, the loss of accuracy is not detailed studied.…”

Scalable and efficient graph traversal on high-throughput cluster

“…Recently, we have done plenty of graph processing research on shared-memory systems and graph-specific accelerators (Yan et al 2020(Yan et al , 2019. With the explosive growth of graph data (CAP Communications 2019), the shared-memory (single-node) systems can no longer achieve high performance for large-scale graphs due to the limited memory capacity.…”