A design methodology for application-specific networks-on-chip

Abstract

With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networkson-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.

Variable-Width Datapath for On-Chip Network Static Power Reduction

“…We observe a significant total power reduction for low loads of approximately 33% for ABN simple. Compared to the synthetic traffic patterns shown earlier, application traffic is often bursty and can create hotspots [46,8,41,18,51,2,16]. Hotspots exacerbate the impact of the lack of flexibility flits have in choosing subnetworks after injection, as shown in Figure 1.…”

“…Variations in application behavior can be important; past work has observed that application demands can vary substantially, and also applications tend to not load the network evenly in both space and time [46,8,41,18,51,2,16]. For example, average injection rates do not exceed 7% for PARSEC benchmarks, although the maximum channel utilization can be 43% [18,2,16,5].…”

Efficient simulation and modelling of non-rectangular NoC topologies

“…A number of papers on constructing irregular network topologies [4], [5], [6], [7] and developing NoC simulators [8], [9], [10], [11], [12] have been published in the past decade. Several design methods were proposed for constructing either special irregular topologies: Ring, Octagon and 2-hop or custom irregular networks tailored to specific applications.…”

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

“…Following the method we presented in an earlier publication, 8 we based the comparisons on Spice simulations of network components in Cadence Spectre, and cycle-accurate simulations for the whole NoC in the OPNET network simulator. As the results in Table 2 show, the MPSoC using the traditional interconnect can only process 22 frames per second, whereas DWP can process 27 frames per second-23 percent higher.…”