Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

Xu, Jiang; Wolf, Wayne; Zhang, Wei

doi:10.1109/mm.2009.40

Cited by 9 publications

(5 citation statements)

References 8 publications

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“…Xu et al built DDR Wave-Pipelined (DWP) links interconnecting asynchronously NoC router ports to reduce the number of link-wires [36]. A router converts the data to be transmitted through a DWP link from SDR to DDR format by sending odd bits on the positive level of the clock and even bits on the negative level of the clock.…”

Section: Related Workmentioning

confidence: 99%

DDRNoC

Ejaz

Papaefstathiou

Sourdis

2018

ACM Trans. Archit. Code Optim.

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This article introduces DDRNoC, an on-chip interconnection network capable of routing packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal), which exhibits significant slack. DDRNoC capitalizes on this observation, allowing two flits per cycle to share the same datapath. Thereby, DDRNoC achieves higher throughput than a Single Data Rate (SDR) network. Alternatively, using lower voltage circuits, the above slack can be exploited to reduce power consumption while matching the SDR network throughput. In addition, DDRNoC exhibits reduced clock distribution power, improving energy efficiency, as it needs a slower clock than a SDR network that routes packets at the same rate. Post place and route results in 28nm technology show that, compared to an iso-voltage (1.1V) SDR network, DDRNoC improves throughput proportionally to the SDR datapath slack. Moreover, a low-voltage (0.95V) DDRNoC implementation converts that slack to power reduction offering the 1.1V SDR throughput at a substantially lower energy cost. CCS Concepts: • Hardware → Network on chip; Buses and high-speed links; Interconnect; System on a chip; Application specific integrated circuits; • Computer systems organization → Interconnection architectures;

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Section: Related Workmentioning

confidence: 99%

DDRNoC

Ejaz

Papaefstathiou

Sourdis

2018

ACM Trans. Archit. Code Optim.

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“…In such schemes, source-synchronous 1 wave-pipeline data transfers with transceiver designs are efficiently used to combat multiple-clock-cycle multi-Gb/s transmissions in global (inter-router) links [9], [11], [14]- [17]. An early study presented in [16] reported that the on-chip wave-pipeline approach, used in global interconnections, offers high performance, while using a smaller area and being more energy-efficient than the pipeline approaches using latches or flip-flops.…”

Section: Motivation and Contributionmentioning

confidence: 99%

Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip

Pham

Mau

Kim

2012

IEEE Trans. VLSI Syst.

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It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The proposed circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead-and live-lock free dynamic path-setup scheme and can achieve high bandwidth and high area and energy efficiency. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch in a four-metal-layer 0.18-m CMOS standard-cell technology can yield an aggregate data bandwidth of up to 73.84 Gb/s, while occupying only a modest area of 0.0315 mm 2 . The synthesizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.

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“…H.264 is an ITU-T recommended multimedia standard with improved coding efficiency and network-friendly design [17]. It has been adopted by new storage standards, such as Blue-ray and HD DVD, and is a promising candidate for HDTV broadcast.…”

Section: Performance Evaluationmentioning

confidence: 99%

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems

Liu

et al. 2011

IEEE Trans. Parallel Distrib. Syst.

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Task graph scheduling on multiprocessor systems is a representative multiprocessor scheduling problem. A solution to this problem consists of the mapping of tasks to processors and the scheduling of tasks on each processor. Optimal solution can be obtained by exploring the entire design space of all possible mapping and scheduling choices. Since the problem is NP-hard, scalability becomes the main concern in solving the problem optimally. In this paper, a SAT-based optimization framework is proposed to address this problem, in which SAT solver is enhanced by integrating with a scheduling analysis tool in a branch and bound manner to prune the solution space efficiently. Performance evaluation results show that our technique has average performance improvement in more than an order of magnitude compared to state-of-the-art techniques. We further build a cycle-accurate network-on-chip simulator based on SystemC to verify the effectiveness of the proposed technique on realistic multiprocessor systems.

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Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

Cited by 9 publications

References 8 publications

DDRNoC

DDRNoC

Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems

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