This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low-and high-fidelity blackbox functions separately. The nonlinear map between the lowfidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low-and highfidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect.
A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dualmodular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.
A dual-output design of inverter chain that is hardened against P-hit single-event transient (SET) is proposed in this paper. The output nodes of the proposed inverter chain are hardened by dual-output topological structure design and stacked PMOSs with isolation. The simulation results based on a 65 nm CMOS technology suggest that the proposed design can eliminate SET pulse significantly. In comparison with the conventional inverter chain and inverter chain using the source-isolation technique, the proposed design is capable of maintain the output steadily irrespective of whether an ion hits "0" or hits "1", i.e., the struck node is at logic "0" or logic "1". Besides, the SET pulse occurring at any stage of inverter chains with the proposed methodology will not disturb the final output, as long as it does not occur at the final stage.
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