Minimizing the number of delay buffers in the synchronization of pipelined systems

Survey on Placement and Routing for Field-Coupled Nanocomputing

“…The approach [46] is similar to [36], where for zone partitioning, they use the algorithm presented in [47] to solve the minimum buffer insertion problem for a pipelined circuit. The solution deems acceptable if the column height variation is low; otherwise, the graph is perturbed.…”

CHAMPION: A Software Design Environment for Adaptive Computing Systems and Application Specific Integrated Circuits (ASICs)

“…To solve the buffer minimization problem using the algorithm proposed in [10], the system has to be represented using a signal flow graph (SFG) in which each processing module is represented as a node and each data path between the modules is represented as a directed edge. The weight of the edge directed from node u (corresponding to processing module P u ) to node v (corresponding to processing module P v ) is an unknown delay variable.…”

“…The second representation can be obtained by inserting a virtual node, VI, with zero processing time as in Figure 14c. Another representation, which is proposed in [10], is shown in Figure 14d. This representation uses a binary tree structure which systematically introduces virtual nodes to the SFG.…”

“…The use of a binary tree structure in representing the hyperarc can greatly exploit the buffer sharing property. To exploit the buffer sharing property fully, an algorithm must be used to arrange the processing nodes in the hyper-arc [10]. Different arrangements of the processing nodes driven by a hyper-arc may vary the total number of buffers along the hyper-arc because each arrangement may cause a different length delay buffer to be shared among the nodes driven by the hyper-arc.…”

“…In [10], it is shown that the constraint matrix of the ILP problem in equations (3) through (5) satisfies the definition of unimodularity. Therefore the ILP problem can be reduced to an LP problem [11].…”