Survey on Placement and Routing for Field-Coupled Nanocomputing

Formigoni, Ruan Evangelista; Ferreira, Ricardo; Nacif, José Augusto M.

doi:10.29292/jics.v16i1.480

Cited by 8 publications

(5 citation statements)

References 45 publications

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“…A soluc ¸ão paralela usa várias memórias e uma soluc ¸ão de sobreposic ¸ão de escrita para maximizar o desempenho, com a execuc ¸ão de cada iterac ¸ão do SA em 2 ciclos de relógio. Trabalhos futuros irão avaliar a integrac ¸ão com algoritmo de roteamento em hardware e também a validac ¸ão para posicionamentos em nanotecnologias [Formigoni et al 2019].…”

Section: Conclusãounclassified

Simulated Annealing em Hardware com Múltiplas Threads em Pipeline para Posicionamento em CGRAs

Penha

Silva²,

Canesche³

et al. 2022

Anais Do XXIII Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2022)

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O uso de aceleradores com paralelismo espacial, como os CGRAs, são soluções promissoras em desempenho e eficiência energética. O desempenho dos CGRAs dependem dos compiladores para explorar o paralelismo das aplicações, sendo o mapeamento da aplicação um dos grandes desafios. A primeira etapa deste processo é o posicionamento, cuja eficiência impacta diretamente nos passos seguintes que são o roteamento e o escalonamento. Este trabalho apresenta uma implementação em hardware, usando field-programmable gate arrays (FPGA), para o algoritmo Simulated Annealing (SA). Os resultados mostram uma aceleração de 7 a 30 vezes em relação ao estado da arte sem sacrificar a qualidade da solução, podendo ser de 70 a 300 vezes mais rápido com o uso de múltiplas unidades de posicionamento. O algoritmo foi implementado em pipeline com múltiplas threads para esconder a latência, onde uma iteração completa do SA executa em apenas dois ciclos de relógio do FPGA.

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Section: Conclusãounclassified

Simulated Annealing em Hardware com Múltiplas Threads em Pipeline para Posicionamento em CGRAs

Penha

Silva²,

Canesche³

et al. 2022

Anais Do XXIII Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2022)

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“…On the other hand, the ortho is a heuristic algorithm that doesn't ensure the optimal circuit solution and is restricted to only one clock scheme but can generate feasible results for more complex circuits. Ropper [54] is another framework for placement an routing of FCN circuits.…”

Section: A Field-coupled Nanocomputingmentioning

confidence: 99%

Design Automation for Emerging Technologies

Paranaiba

Oliveira

Marks³

et al. 2022

JICS

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After the continuous development of CMOS technology driven by transistor miniaturization and Moore’s law, the scientific community is witnessing the exploration of emerging paradigms to find new ways to develop computational systems. This paper presents critical concepts for understanding some of these new nanocomputing technologies, specifically field-coupled, quantum-dot cellular automata, nanomagnetic logic, silicon dangling bounds, photonic crystal logic, and DNA computing. Next, it shows emerging design automation tools for each of these areas and how they can be applied to support the development of new computing systems. The level of maturity and production speed of solutions achieved by conventional silicon technology thanks to very efficient electronic design automation (EDA) is remarkable. However, here we are dealing with technologies still in their infancy. Therefore, improvements in design automation tools are undoubtedly a way to accelerate the growth of new substrate alternatives and modern applications.

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“…Due to the lack of automatic design tools for circuits in QCA, the design process is still mainly manually completed. However, it can be foreseeable that combined with a corresponding algorithm, such as the Ropper algorithm in Formigoni et al, 34 the design process may be completed automatically.…”

Section: Case Studiesmentioning

confidence: 99%

Module‐based design method using clocking scheme for quantum‐dot cellular automata

Deng

Xie

Zhang

et al. 2021

Circuit Theory & Apps

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Quantum-dot cellular automata (QCA) is a field-coupled nanotechnology with unique computing paradigms to be one of the strong alternatives to replace the traditional complementary metal oxide semiconductor (CMOS) in the future in theory. With the development of its fabrication technique and increasing circuit scale, the modular design method of QCA circuits is promoted, which consists at least of two connotations: designing appropriate modules for circuits and allocating applicable clock to circuits. In this paper, a module-based design method using a clocking scheme (MCS) in QCA is proposed, which can be categorized into the modular design methodology. A complete module

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Survey on Placement and Routing for Field-Coupled Nanocomputing

Cited by 8 publications

References 45 publications

Simulated Annealing em Hardware com Múltiplas Threads em Pipeline para Posicionamento em CGRAs

Simulated Annealing em Hardware com Múltiplas Threads em Pipeline para Posicionamento em CGRAs

Design Automation for Emerging Technologies

Module‐based design method using clocking scheme for quantum‐dot cellular automata

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