Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.
Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit designs. The circuits in QCA have been extensively studied, which suffer from negative impacts due to the limits of the manual design process, even for a modest complexity. In the process of QCA circuit design, the problems caused by clock distribution and long transmission lines have to be considered. In order to solve such problems, some researchers have proposed several clock schemes and expected to realise electronic design automation. These clock schemes, however, have drawbacks; the most important one is the limitation of flexibility on designing complex circuits. In this regard, this study proposes a convenient, flexible, and efficient (CFE) clocking scheme by using diamond structures for clock zones, each of which has the same neighbouring clock zone and four information transmission directions. It has main advantages of existing clocking schemes and can commendably increase the flexibility in circuit design process. In order to show the suitability of the proposed CFE scheme using standard clock mechanism in QCA, several types of circuits proposed in this study reveal its advantages in comparison with an existing state-of-the-art clocking scheme.
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