An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis

Zhang, Shuhan; Lyu, Wenlong; Yang, Fan; Yan, Changhao; Zhou, Dian; Zeng, Xuan; Hu, Xiangdong

doi:10.1145/3316781.3317765

Cited by 45 publications

(12 citation statements)

References 22 publications

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“…The PF function can help to prioritize data points when the predictive means of all constraints satisfy design specifications and the expected constraint violation value is zero. To achieve a more extensive coverage over the Pareto front of exploration and exploitation, we also introduce the naive constraint violation measurement in equation (12) to encourage exploration. In other words, we select query points by sampling B data points from the Pareto front of the following equation:…”

Section: A Seek the First Feasible Pointmentioning

confidence: 99%

An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble

Zhang

Yang

Yan

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Bayesian optimization is a promising methodology for analog circuit synthesis. However, the sequential nature of the Bayesian optimization framework significantly limits its ability to fully utilize real-world computational resources. In this paper, we propose an efficient parallelizable Bayesian optimization algorithm via Multi-objective ACquisition function Ensemble (MACE) to further accelerate the optimization procedure. By sampling query points from the Pareto front of the probability of improvement (PI), expected improvement (EI) and lower confidence bound (LCB), we combine the benefits of state-of-theart acquisition functions to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem. Based on this batch design, we further adjust the algorithm for the constrained optimization problem. By dividing the optimization procedure into two stages and first focusing on finding an initial feasible point, we manage to gain more information about the valid region and can better avoid sampling around the infeasible area. After achieving the first feasible point, we favor the feasible region by adopting a specially designed penalization term to the acquisition function ensemble. The experimental results quantitatively demonstrate that our proposed algorithm can reduce the overall simulation time by up to 74× compared to differential evolution (DE) for the unconstrained optimization problem when the batch size is 15. For the constrained optimization problem, our proposed algorithm can speed up the optimization process by up to 15× compared to the weighted expected improvement based Bayesian optimization (WEIBO) approach, when the batch size is 15.

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Section: A Seek the First Feasible Pointmentioning

confidence: 99%

An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble

Zhang

Yang

Yan

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…By carefully choosing the covariance function one can embed the model with prior knowledge about the objective function to improve the predicting accuracy of the model [34]. A regression GP model is built from a training set D(X, y) where X = {x 1 , x 2 , ..., x N } denotes the input vectors with N observations, and y represents the corresponding outputs [34,35].…”

Section: Gaussian-processes-based Regression Modelsmentioning

confidence: 99%

Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

et al. 2020

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Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

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“…Moreover, with the increase in AMS circuits complexity, increasing nonlinearity stands out as major factor limiting the capabilities of performance modeling and optimization. Hence, performance optimization techniques relying on nonparametric surrogate models and Bayesian optimization frameworks have been recently proposed [31,83]. These surrogate models are typically Gaussian Processes, and Bayesian optimization is used to find optimal values given a black-box function.…”

Section: Performance Optimizationmentioning

confidence: 99%

“…The new data collected at each step augments the training dataset to retrain a probabilistic surrogate model that approximates the black-box function. Such iterative sampling scheme contributes directly to the accuracy of the surrogate model and guides the iterative global optimization process [31,83].…”

Section: Performance Optimizationmentioning

confidence: 99%

Dealing with Aging and Yield in Scaled Technologies

Alawieh

Hsu

et al. 2020

Dependable Embedded Systems

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This chapter reviews recent practices of tackling aging and yield issues in VLSI design related to shrinking technology processes. Different fundamental effects such as device aging, interconnect electromigration, and process variations are investigated with the state-of-the-art techniques for modeling and optimization. The presented techniques vary from analytical approaches to machine learning, and often require cross-layer information feedback for robust design cycles.

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An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis

Cited by 45 publications

References 22 publications

An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble

An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble

Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

Dealing with Aging and Yield in Scaled Technologies

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