A single event upset tolerant latch with parallel nodes

Abstract

A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dualmodular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.

TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation

“…To tolerate node upsets, in recent years, researchers proposed many designs, such as memory cells [4][5], flip-flops [6][7], and latches [8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Although most of the existing latch designs are hardened against node upsets, they still suffer from severe problems.…”

“…Although most of the existing latch designs are hardened against node upsets, they still suffer from severe problems. First, some latch designs [8][9][12][13] are only SNU-tolerant, which means that any of them has at least one node-pair that cannot effectively tolerate a 2NU. Second, some latch designs [10][11][14][15][16][17] are 2NU-tolerant.…”

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

“…To mitigate SNUs and DNUs, radiation hardening by design (RHBD) is a widely employed approach. Using RHBD, many novel storage elements, such as latches [5][6][7][8], static random access memories (SRAMs) [9][10][11][12], and flip-flops (FFs) [13][14][15][16][17][18][19]23] have been proposed. Among them, dual-interlocked storage-cells (DICEs) are widely used [20].…”

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

“…To mitigate SNUs, DNUs, TNUs, and/or SETs, by means of radiation-hardening-by-design (RHBD) approaches, many hardened storage cells such as static random access memories (SRAMs) [9][10][11][12], flip-flops [13][14][15][16], and latches [5][6][7][8][17][18][19][20][21][22][23][24][25][26][27], have been proposed. This paper focuses on latches.…”

“…1) They cannot provide complete TNU-tolerability [17][18][19][20][21][22][23][24][25][26] since there is at least one counterexample that an invalid value will be retained if any of them suffers from a TNU. 2) They cannot provide SET-filterability [5-8, 17-18, 21, 23-27] since SETs can unfortunately propagate to the output from the input for any of them.…”