Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

Yan, Aibin; Xu, Zhelong; Cui, Jie; Ying, Zuobin; Huang, Zhengfeng; Liang, Hongbin; Girard, Patrick; Wen, Xiaoqing

doi:10.1109/iscas45731.2020.9181135

Cited by 5 publications

(10 citation statements)

References 23 publications

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Section: Figurementioning

confidence: 98%

“…As can be seen, the maximum pulse width of SET decreases as the voltage supply increases (higher conductivity of the transistors) [7]. This dependency should be considered when it is necessary to suppress the SET pulse in sensitive applications [30][31][32]. It is worth mentioning that in [24], aiming at masking SET, a Schmitt Trigger Inverter is used in transparent mode; however, it has a large impact on delay because of the hysteresis property.…”

Section: Figurementioning

confidence: 99%

“…Furthermore, as PDP is a figure of merit showing the total performance of D-latches and, in particular, commonly used to evaluate hardened D-latches [7,30], a PDP comparison of the proposed and previous D-latches is shown in Figure 9. As can be seen, the PDP of the proposed D-latch is even slightly better than that of the Static D-latch, with a 3.67% improvement.…”

Section: Pdpmentioning

confidence: 99%

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Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

et al. 2021

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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Section: Figurementioning

confidence: 98%

Section: Figurementioning

confidence: 99%

Section: Pdpmentioning

confidence: 99%

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Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

et al. 2021

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“…Therefore, this paper mainly focuses on radiation hardening against SNUs and DNUs. To tolerate SNUs and DNUs with the RHBD approach, many novel structures, such as latches [5][6][7][8][9], static random-access memories (SRAMs) [10][11] and FFs [12][13][14][15][16][17][18], have been proposed. Among them, DICEs are widely used [19].…”

Section: Introductionmentioning

confidence: 99%

“…Because conventional latches usually can be severely affected by radioactive particles, the conventional FFs composed of these latches are vulnerable to radioactive particles, which can induce SNUs and DNUs. To tolerate SNUs and DNUs with the RHBD approach, a series of FFs, such as those in [12][13][14][15][16][17][18], have been proposed. However, these FFs still suffer from some problems in terms of reliability and overhead issues:…”

Section: Introductionmentioning

confidence: 99%

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications

Yan

Chen

Song

et al. 2022

Proceedings of the Great Lakes Symposium on VLSI 2022

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This paper proposes a novel sextuple cross-coupled dualinterlocked-storage-cell (DICE) based double-node-upset (DNU) recoverable and low-delay flip-flop (FF), namely SCDRL-FF, for aerospace applications. The SCDRL-FF mainly consists of sextuple cross-coupled DICEs controlled by clock-gating. The use of clockgating based DICEs significantly reduces the CLK-Q transmission delay of the SCDRL-FF. Through the redundant and interlocked clock-gating based DICEs, the SCDRL-FF can provide complete DNU recoverability. Simulation results demonstrate the DNU recoverability of the SCDRL-FF and a 65% delay reduction on average compared with the state-of-the-art hardened FFs. The low delay overhead makes the proposed SCDRL-FF effectively applicable to high-performance applications and the DNU recoverability makes the proposed SCDRL-FF also suitable for aerospace applications.

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The New Small Wheel electronics

et al. 2023

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The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm2 at the expected HL-LHC luminosity of ℒ = 7.5 × 1034 cm-2 s-1. The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

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Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

Cited by 5 publications

References 23 publications

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications

The New Small Wheel electronics

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