A measurement methodology involving the synchronous switching of gate to source voltage and drain to source voltage (VDS) was proposed for determining the shift of threshold voltage after an AlGaN/GaN heterostructure transistor endures high VDS off-state stress. The measurement results indicated slow electron detrapping behavior. The trap level was determined as (EC – 0.6 eV). Simulation tool was used to analyze the measurement results. The simulation results were consistent with the experimental results; and a relationship between the buffer trap and threshold voltage shift over time was observed.
This study examined the correlation between the off-state leakage current and dynamic on-resistance (RON) transients in AlGaN/GaN heterostructure field-effect transistors (HFETs) with and without a gate insulator under various stress conditions. The RON transients in a Schottky-gate HFET (SGHFET) and metal-insulator-semiconductor HFET (MISHFET) were observed after applying various amounts of drain-source bias stress. The gate insulator in the MISHFET effectively reduced the electron injection from the gate, thereby mitigating the degradation in dynamic switching performance. However, at relaxation times exceeding 10 ms, additional detrapping occurred in both the SGHFET and MISHFET when the applied stress exceeded a critical voltage level, 50 V for the SGHFET and 60 V for MISHFET, resulting in resistive leakage current build-up and the formation of hot carriers. These high-energy carriers acted as ionized traps in the channel or buffer layers, which subsequently caused additional trapping and detrapping to occur in both HFETs during the dynamic switching test conducted.
A measurement methodology involving high-voltage capacitance-voltage (C-V ) was proposed to determine the trapping profile of a stressed AlGaN/GaN heterostructure field-effect transistor (HFET). Comparing the curves between initial (device without stress) and stressed (device with stress)
C-V measurements revealed that the transient behavior was dominated by ionized acceptor-like traps, and the trapping profile within the high drain-to-source OFF-state stressed AlGaN/GaN HFET could be deduced.Index Terms-AlGaN/GaN heterostructure field-effect transistors (HFETs), current collapse, transient capacitancevoltage (C-V ) measurement.
Publisher's Note: "The behavior of off-state stress-induced electrons trapped at the buffer layer in AlGaN/GaN heterostructure field effect transistors" [Appl. Phys. Lett. 104, 033503 (2014)]
A fabrication method of 2-D nanostructure materials applied for forming nanothick SOI materials without using post-thinning processes is presented in this paper. The thickness of SOI layer is precisely controlled by a polysilicon layer as a sacrificial layer in the implantation step to acquire a desirable implant depth. Polysilicon layer was initially deposited on the thermal oxidized surface of silicon wafer prior to the ion implantation step with 4×10 16 /cm -2 , 160KeV, H 2 + ions. The as-implanted wafer was contained a hydrogen-rich buried layer which depth from the top surface is less than 100 nm. Before this as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet etching method. A nanothick silicon layer was then successfully transferred onto a handle wafer under 10-minute microwave irradiation after the bonding step. The thickness of the final transferred silicon layer was 100 nm measured by transmission electron microscopy (TEM).
In this study, conventional multiple-frequency capacitance-voltage (C-V) curves of a metal-insulator-semiconductor structure were modified into barrier capacitance-barrier voltage (C br -V br ) curves to study the interface state of an Al 2 O 3 /III-N interface. By eliminating the contribution of a serially connected insulator capacitance (C i ), the variation of C br as a function of V br could be obtained for determining the interface-state-caused dispersion precisely. This technique was used to deduce the distribution of energy-level-dependent D it and to investigate the influence of thermal oxidization on an Al 2 O 3 /AlGaN/GaN heterostructure with an in situ grown AlN/GaN cap layer. The oxidization process was performed prior to Al 2 O 3 deposition. Depositing an Al 2 O 3 layer on an oxidized wafer by using an atomic layer deposition system can considerably reduce the dispersion behavior among frequencydependent C br -V br curves. By determining the amount of frequency dispersion among the C br -V br curves, the distribution of D it was determined to be in the range between 1.4 × 10 12 and 2.6 × 10 13 eV −1 • cm −2 , which was an approximately one-order-of-magnitude reduction compared with a structure that was not subjected to the oxidization process.
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