Trap-Profile Extraction Using High-Voltage Capacitance–Voltage Measurement in AlGaN/GaN Heterostructure Field-Effect Transistors With Field Plates

Liao, Wen-Chia; Chyi, Jen‐Inn; Hsin, Yue-Ming

doi:10.1109/ted.2015.2395720

Cited by 14 publications

(3 citation statements)

References 15 publications

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“…It has been demonstrated that input capacitance (C ISS ) which includes gate-to-source capacitance (C GS ) and gate-to-drain capacitance (C GD ) plays an important role in switching loss calculation and gate driver evaluation of GaN power HEMT devices [2,3]. So far, extensive works have been carried out for investigating the C ISS in several normally-on AlGaN/GaN HEMTs [4][5][6][7][8]. In the normally-on HEMT samples adopting metal-insulator-semiconductor or Schottky contact gate, the depletion of electrons dominates the variation of C GS and C GD [7,8].…”

Section: Introductionmentioning

confidence: 99%

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

Wang¹,

Chen²,

Li³

et al. 2020

J. Phys. D: Appl. Phys.

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In this paper, input capacitance (CISS) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. CISS includes gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD). In comparison with the normally-on HEMTs, it is found that the phenomenon of CISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of CISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of CGS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing CGS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of CGD. Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on CISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the CISS related capacitance design and gate driver optimization of the devices.

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Section: Introductionmentioning

confidence: 99%

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

Wang¹,

Chen²,

Li³

et al. 2020

J. Phys. D: Appl. Phys.

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“…The schematic diagrams of the equivalent circuit in p-GaN gate HEMTs under gate floating are shown in figures 7(a) and (b) for Schottky and ohmic gate devices, respectively [33,34]. Because the gate electrode is floating, the original C GS and C GD will be replaced with C G ′ S and C G ′ D by only considering the p-GaN layer to the source and the drain.…”

Section: Resultsmentioning

confidence: 99%

I–V Characteristics of E-mode GaN-based transistors under gate floating

Qin¹,

Tsai²,

Chen³

et al. 2022

Semicond. Sci. Technol.

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This study investigates the I-V behaviors of various E-mode GaN-based transistors under gate floating and zero gate bias. The p-GaN gate HEMTs, Gate injection transistors (GIT), and Cascode GaN FETs have been adopted and compared. The high off-state drain current is observed under gate floating except for Cascode GaN FETs based on the measured I-V characteristics. The off-state drain current of p-GaN gate HEMT is up to 0.8 mA under gate floating at a drain bias of 6 V, which is about 107 times larger than zero gate bias. The devices will induce false-turn-on and reverse conduction loss during switching under gate floating due to the capacitance charging effect between the drain and the gate electrodes. The mechanism of the capacitance charging effect is discussed using the equivalent circuit of p-GaN gate HEMTs and confirmed by Silvaco TCAD simulation.

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“…Publications with analysis based on the electron trapping by surface states and epitaxial defects have been proposed (4)(5)(6). Suitable fieldplate design is necessary to reduce the high electric-field at the edge of gate electrode to relieve the surface states issue and improve current collapse and breakdown voltage (7). Other surface structures were investigated including in-situ SiN layer, AlN cap layer, and LPCVD SiN layer (8)(9)(10).…”

Section: Introductionmentioning

confidence: 99%

AlGaN/GaN High Electron Mobility Transistors with a p-Type GaN Cap Layer

Tsai¹,

Chiang²,

Zhong³

et al. 2018

ECS Trans.

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In this work, AlGaN/GaN HEMTs with different types of p-GaN cap layers were fabricated and investigated. The p-GaN cap layer used in this study was for passivation study instead of forming enhancement-mode operation. The differences in p-GaN cap layers were Mg-doping concentration (110 19 and 310 19 cm -3 ) and thickness (5 and 8 nm). Device with p-GaN cap of 8-nm and Mgdoping of 310 19 cm -3 showed the lowest gate leakage current, highest on/off current ratio (1.02×10 6 ), highest breakdown voltage and least current collapse characteristics.

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Trap-Profile Extraction Using High-Voltage Capacitance–Voltage Measurement in AlGaN/GaN Heterostructure Field-Effect Transistors With Field Plates

Cited by 14 publications

References 15 publications

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

I–V Characteristics of E-mode GaN-based transistors under gate floating

AlGaN/GaN High Electron Mobility Transistors with a p-Type GaN Cap Layer

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