Emerging non-volatile memories have been proposed for a wide range of applications, from easing the von-Neumann bottleneck to neuromorphic applications. Specifically, scalable RRAMs based on Pr1-xCaxMnO3 (PCMO) exhibit analog switching have been demonstrated as an integrating neuron, an analog synapse, and a voltage-controlled oscillator. More recently, the inherent stochasticity of memristors has been proposed for efficient hardware implementations of Boltzmann Machines. However, as the problem size scales, the number of neurons increases and controlling the stochastic distribution tightly over many iterations is necessary. This requires parametric control over stochasticity. Here, we characterize the stochastic Set in PCMO RRAMs. We identify that the Set time distribution depends on the internal state of the device (i.e., resistance) in addition to external input (i.e., voltage pulse). This requires the confluence of contradictory properties like stochastic switching as well as deterministic state control in the same device. Unlike ‘stochastic-everywhere’ filamentary memristors, in PCMO RRAMs, we leverage the (i) stochastic Set in negative polarity and (ii) deterministic analog Reset in positive polarity to demonstrate 100× reduced Set time distribution drift. The impact on Boltzmann Machines’ performance is analyzed and as opposed to the “fixed external input stochasticity”, the “state-monitored stochasticity” can solve problems 20× larger in size. State monitoring also tunes out the device-to-device variability effect on distributions providing 10× better performance. In addition to the physical insights, this study establishes the use of experimental stochasticity in PCMO RRAMs in stochastic recurrent neural networks reliably over many iterations.
Liquid State Machine (LSM) is a brain-inspired architecture used for solving problems like speech recognition and time series prediction. LSM comprises of a randomly connected recurrent network of spiking neurons. This network propagates the non-linear neuronal and synaptic dynamics. Maass et al. have argued that the non-linear dynamics of LSMs is essential for its performance as a universal computer. Lyapunov exponent (µ), used to characterize the non-linearity of the network, correlates well with LSM performance. We propose a complementary approach of approximating the LSM dynamics with a linear state space representation. The spike rates from this model are well correlated to the spike rates from LSM. Such equivalence allows the extraction of a memory metric (τM ) from the state transition matrix. τM displays high correlation with performance. Further, high τM system require lesser epochs to achieve a given accuracy. Being computationally cheap (1800× time efficient compared to LSM), the τM metric enables exploration of the vast parameter design space. We observe that the performance correlation of the τM surpasses the Lyapunov exponent (µ), (2 − 4× improvement) in the high-performance regime over multiple datasets. In fact, while µ increases monotonically with network activity, the performance reaches a maxima at a specific activity described in literature as the edge of chaos. On the other hand, τM remains correlated with LSM performance even as µ increases monotonically. Hence, τM captures the useful memory of network activity that enables LSM performance. It also enables rapid design space exploration and fine-tuning of LSM parameters for high performance.
Pr1–x
Ca
x
MnO3 (PCMO)-based
resistance random access memory
(RRAM) is attractive in large-scale memory and neuromorphic applications
as it is nonfilamentary and area scalable and has multiple resistance
states along with excellent endurance and retention. The PCMO RRAM
exhibits area-scalable resistive switching when in contact with the
reactive electrode. The interface redox reaction-based resistance
switching is observed electrically. Yet, whether the resistance change
occurs near the reactive interface or spread over the entire bulk
is largely debated. Essentially, a two-terminal device is unable to
provide direct evidence of the resistance change region in the PCMO
RRAM. In this paper, we propose and experimentally demonstrate a three-terminal
RRAM (3T-RRAM) device in which a thin third terminal (∼20 nm)
is inserted laterally in close proximity to a typical vertical two-terminal
RRAM device of PCMO thickness ∼80 nm. It is well known that
the reactive interface participates in the resistive switching. However,
using the 3T-RRAM, we demonstrate that the resistance change also
occurs in the region near the inert electrode. We further show that
the resistance measured by T3 is exclusively sensitive to the region
near the inert electrode as opposed to the reactive electrode. Finally,
the highly symmetric space charge limited current (SCLC) characteristics
with polarity at various resistance levels, typical of two-terminal
RRAM, are undisturbed because of the slightly adjacent placement of
the nanoscale inert third terminal while providing resistance change
read sensitivity. It is the first time that an interface redox and
bulk SCLC-based resistance change has been experimentally shown as
correlated and consistent, enabled by the third terminal of the RRAM.
Such a study details a critical understanding of the device which
can enable the design and development of PCMO RRAM for large memory
and neuromorphic computing applications.
The neural network enables efficient solutions for Nondeterministic Polynomial-time (NP) hard problems, which are challenging for conventional von Neumann computing. The hardware implementation, i.e., neuromorphic computing, aspires to enhance this efficiency by custom hardware. Particularly, NP hard graphical constraint optimization problems are solved by a network of stochastic binary neurons to form a Boltzmann Machine (BM). The implementation of stochastic neurons in hardware is a major challenge. In this work, we demonstrate that the high to low resistance switching (set) process of a PrxCa1−xMnO3 (PCMO) based RRAM (Resistive Random Access Memory) is probabilistic. Additionally, the voltage-dependent probability distribution approximates a sigmoid function with 1.35%–3.5% error. Such a sigmoid function is required for a BM. Thus, the Analog Approximate Sigmoid (AAS) stochastic neuron is proposed to solve the maximum cut—an NP hard problem. It is compared with Digital Precision-controlled Sigmoid (DPS) implementation using (a) pure CMOS design and (b) hybrid (RRAM integrated with CMOS). The AAS design solves the problem with 98% accuracy, which is comparable with the DPS design but with 10× area and 4× energy advantage. Thus, ASIC neuro-processors based on novel analog neuromorphic devices based BM are promising for efficiently solving large scale NP hard optimization problems.
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