Heterogeneous MPSoC design where flexible programmable cores are combined with optimized HW co-processors is a quite complex and challenging task. In this paper, we present a systemlevel design flow that uses a single functional reference for modeling both HW and SW. The models follow an interfacecentric design approach based on the TTL interface (Task Transaction Level). TTL models are applied at all three abstraction levels of the design flow: functional, architecture and implementation level. The TTL model at the functional level serves as the functional reference. HW implementations are generated from refined TTL models by behavioral synthesis tooling. Likewise, SW implementations are supported by source code transformations. Both the HW and SW implementations are verified against the functional reference. Details of the complete flow are presented in the paper through an MP3 case study.
This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.
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