A Unified System-Level Modeling and Simulation Environment for MPSoC design: MPEG-4 Decoder Case Study

Reyes, Víctor; Kruijtzer, Wido; Bautista, Tomás; Alkadi, G.; Núñez, Antonio

doi:10.1109/date.2006.243831

Cited by 18 publications

(14 citation statements)

References 14 publications

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“…Thanks to the Y-chart paradigm, the mapping step is reduced to a task to processing element assignment, whereas communication is strictly handled by the task transaction level (TTL) interface [227]. The technology has been successfully applied to multimedia applications [228]. In addition, a path to the final hardware implementation has been envisioned [229].…”

Section: Simulation-based Approachesmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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Section: Simulation-based Approachesmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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“…TTL-based approaches [14,15] does not propose algorithmics for the synthesis of a scheduled software which thus resorts to the designer exploration effort [14,15], and does not handle software-level design exploration [16].…”

Section: Related Workmentioning

confidence: 99%

A scheduler synthesis methodology for joint SW/HW design exploration of SoC

Assayad

Yovine

2010

Des Autom Embed Syst

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The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardwarelevel schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs.

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“…Therefore, these techniques can be utilized right from the start of the design cycle and do not need to be delayed. Examples for such simulation models described in [10][11][12][13][14][15] and [2]. Recent case studies from industry have proved the capabilities of such abstract simulation models [16].…”

Section: Related Workmentioning

confidence: 99%

Analytical and Simulation-based Design Space Exploration of Software Defined Radios

Kempf

Wallentowitz

Ascheid

et al. 2010

Int J Parallel Prog

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The proposed idea of software defined radios (SDRs) offers the potential to cope with the complexity and flexibility demands of future wireless communication devices. Unfortunately, the tight interaction of software and hardware as well as the high computational requirements make development of SDRs to one of the most challenging tasks system architects are facing today. The main challenge is to select the optimal or a sub-optimal solution within the large design space spread by the many design options. This paper introduces a novel design space exploration framework for particular early development stages. The key contribution is a pre-simulation based mathematical analysis based on synchronous data flow (SDF) graphs in order to take the right software and hardware design decisions. This analysis can be utilized right from the start of the design cycle with only limited knowledge of the final implementation. In addition, the proposed technique seamlessly integrates into an electronic system level (ESL) based simulation framework. This allows for a smooth transition from pure mathematical analysis to the simulation of the final implementation. The practical usage of the framework and its capabilities are highlighted by a case study from a typical SDR design.

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A Unified System-Level Modeling and Simulation Environment for MPSoC design: MPEG-4 Decoder Case Study

Cited by 18 publications

References 14 publications

Multiprocessor Systems on Chip

Multiprocessor Systems on Chip

A scheduler synthesis methodology for joint SW/HW design exploration of SoC

Analytical and Simulation-based Design Space Exploration of Software Defined Radios

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