A multicast inter-task communication protocol for embedded multiprocessor systems

Reyes, Víctor; Bautista, Tomás; Marrero, G.; Núñez, Antonio; Kruijtzer, Wido

doi:10.1145/1084834.1084901

Cited by 8 publications

(4 citation statements)

References 4 publications

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“…Due to this reason, other important metrics in SoC design such as power consumption and area/cost are not yet included in the analysis presented in this paper. More information about the internal structure of the tool can be found [8,9,10] .…”

Section: Simulation Toolmentioning

confidence: 99%

Real-time visual tracking system modelling in MPSoC using platform based design

et al. 2009

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In this paper, we present the modelling of a real-time tracking system on a Multi-Processor System on Chip (MPSoC). Our final goal is to build a more complex computer vision system (CVS) by integrating several applications in a modular way, which performs different kind of data processing issues but sharing a common platform, and this way, a solution for a set of applications using the same architecture is offered and not just for one application. In our current work, a visual tracking system with real-time behaviour (25 frames/sec) is used like a reference application, and also, guidelines for our future CVS applications development. Our algorithm written in C++ is based on correlation technique and the threshold dynamic update approach. After an initial computational complexity analysis, a task-graph was generated from this tracking algorithm. Concurrently with this functionality correctness analysis, a generic model of multi-processor platform was developed. Finally, the tracking system performance mapped onto the proposed architecture and shared resource usage were analyzed to determine the real architecture capacity, and also to find out possible bottlenecks in order to propose new solutions which allow more applications to be mapped on the platform template in the future.

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Section: Simulation Toolmentioning

confidence: 99%

Real-time visual tracking system modelling in MPSoC using platform based design

et al. 2009

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“…These tasks communicate with the KPN protocol specified in CASSE, the Inter Task Communication Protocol (ITCP) [15] which had to be adapted to be executed in the ARM9 processor. An incremental implementation process was followed in order to replace the different tasks, IDCT, input and output co-processor, with their hardware implementations.…”

Section: From Simulation To Implementationmentioning

confidence: 99%

MPEG-4 ASP SoC receiver with novel image enhancement techniques for DAB networks

et al. 2007

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This paper presents a system for real-time video reception in low-power mobile devices using Digital Audio Broadcast (DAB) technology for transmission. A demo receiver terminal is designed into a FPGA platform using the Advanced Simple Profile (ASP) MPEG-4 standard for video decoding. In order to keep the demanding DAB requirements, the bandwidth of the encoded sequence must be drastically reduced. In this sense, prior to the MPEG-4 coding stage, a preprocessing stage is performed. It is firstly composed by a segmentation phase according to motion and texture based on the Principal Component Analysis (PCA) of the input video sequence, and secondly by a down-sampling phase, which depends on the segmentation results. As a result of the segmentation task, a set of texture and motion maps are obtained. These motion and texture maps are also included into the bit-stream as user data side-information and are therefore known to the receiver. For all bit-rates, the whole encoder/decoder system proposed in this paper exhibits higher image visual quality than the alternative encoding/decoding method, assuming equal image sizes. A complete analysis of both techniques has also been performed to provide the optimum motion and texture maps for the global system, which has been finally validated for a variety of video sequences. Additionally, an optimal HW/SW partition for the MPEG-4 decoder has been studied and implemented over a Programmable Logic Device with an embedded ARM9 processor. Simulation results show that a throughput of 15 QCIF frames per second can be achieved with low area and low power implementation.

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“…Traditional on-chip communication architectures for MPSoC face several issues, such as poor scalability, limited bandwidth, and high power consumption [2] [3]. Networks-on-chip (NoCs) relieve MPSoC of these issues by using modern communication and networking theories.…”

Section: Introductionmentioning

confidence: 99%