CASSE: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip

Reyes, Víctor; Bautista, Tomás; Marrero, G.; Carballo, Pedro P.; Kruijtzer, Wido

doi:10.1109/dsd.2004.1333313

Cited by 24 publications

(20 citation statements)

References 9 publications

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“…Most of the approaches in the embedded systems domain are targeted to the system-level exploration of heterogeneous MP-SoCs [3,4,9,10,11]. Although these efforts are fairly efficient to explore, e.g., the various alternatives for mapping a specific application onto a target MP-SoC architecture, they typically still require significant efforts to (re-)write the scripts that control the evaluation mechanism (analytical model or simulator) during the search through the design space.…”

Section: Related Workmentioning

confidence: 99%

“…Secondly, both tools ensure deadlock-free task mappings and schedules for feasible design points. The interested reader is referred to [2] for an overview of existing system-level simulators, and to [3,4] for more detailed information about CASSE and Sesame.…”

Section: F Simulatormentioning

confidence: 99%

“…At this moment, we have integrated a SystemC-based system-level simulation environment, called CASSE [3], in NASA. Another system-level simulator, called Sesame [4], is in the process of being integrated.…”

Section: F Simulatormentioning

confidence: 99%

“…analytical models or simulation, and 2) the search mechanism to systematically travel through the design space. Both DSE components have received significant research attention during the last decades [3,4,5,6]. For example, system-level simulation is a popular method for evaluating single design points [2].…”

Section: Introductionmentioning

confidence: 99%

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NASA: A generic infrastructure for system-level MP-SoC design space exploration

Jia

Pimentel

Thompson

et al. 2010

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia

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Abstract-System-level simulation and design space exploration (DSE) are key ingredients for the design of multiprocessor system-on-chip (MP-SoC) based embedded systems. The efforts in this area, however, typically use ad-hoc software infrastructures to facilitate and support the system-level DSE experiments. In this paper, we present a new, generic systemlevel MP-SoC DSE infrastructure, called NASA (Non Ad-hoc Search Algorithm). This highly modular framework uses welldefined interfaces to easily integrate different system-level simulation tools as well as different combinations of search strategies in a simple plug-and-play fashion. Moreover, NASA deploys a so-called dimension-oriented DSE approach, allowing designers to configure the appropriate number of, possibly different, search algorithms to simultaneously co-explore the various design space dimensions. As a result, NASA provides a flexible and re-usable framework for the systematic exploration of the multi-dimensional MP-SoC design space, starting from a set of relatively simple user specifications. To demonstrate the distinct aspects of NASA, we also present several DSE experiments in which we, e.g., compare NASA configurations using a single search algorithm for all design space dimensions to configurations using a separate search algorithm per dimension. These experiments indicate that the latter multi-dimensional coexploration can find better design points and evaluates a higher diversity of design alternatives as compared to the more traditional approach of using a single search algorithm for all dimensions.

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Section: Related Workmentioning

confidence: 99%

Section: F Simulatormentioning

confidence: 99%

Section: F Simulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

NASA: A generic infrastructure for system-level MP-SoC design space exploration

Jia

Pimentel

Thompson

et al. 2010

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia

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“…Furthermore the ME and SI can be intensively verified together with the software before pursuing their actual FPGA implementation by using the VP as a system test bench. The VP is built using CASSE [7], which models architectural elements at the higher abstraction level using transaction-level modeling techniques. More details regarding the coprocessor development are described in Section 4.…”

Section: Design Flowmentioning

confidence: 99%

Design, synthesis and verification of a smart imaging core using SystemC

Kruijtzer

Reyes

Gehrke

2005

Des Autom Embed Syst

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In this paper the development of a smart imaging core following a SystemC-based design flow is presented. The smart imaging core integrates an ARM processor and two specific hardware blocks for image processing: a smart imaging coprocessor and a motion estimation coprocessor. A SystemC-based design flow is applied, comprising the design, synthesis and verification and synthesis of the two coprocessors, as well as the development and integration of the embedded software on the smart imaging core. The two coprocessors are successfully modeled and refined from C/C++-based algorithmic descriptions down to architecture reference models using SystemC and TLM concepts. For the RTL implementation of the coprocessor hardware high-level synthesis tools are used. The applied SystemC-based design flow enabled the iterative refinement of the architecture towards an optimal RTL implementation. Furthermore, the use of SystemC TLM supports the integration of fast functional models of the coprocessors on a virtual prototype platform of the target architecture. This virtual prototype is beneficially used during the embedded software development phase.

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Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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CASSE: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip

Cited by 24 publications

References 9 publications

NASA: A generic infrastructure for system-level MP-SoC design space exploration

NASA: A generic infrastructure for system-level MP-SoC design space exploration

Design, synthesis and verification of a smart imaging core using SystemC

Multiprocessor Systems on Chip

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