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Strained silicon induced by the CMOS device process has been considered an important technology for improving the performance of MOSFETs by increasing local carrier mobility in the current channel. In order to evaluate the feasibility of using convergent beam electron diffraction (CBED) in lattice strain determination, high-order Laue zone (HOLZ) lines inside the center disc of a CBED pattern with specific zone axes were kinematically simulated. The intersecting HOLZ lines shift was plotted against the lattice parameter for the determination of uniaxial strain.

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As the IC product scribe line of logic 90nm (L90) technology shrinks from 80µm to 62µm, the wafer quality (W.Q.), will become weak and less distinguishable during the subsequent ASML scanner stepper's photo mask aligning. Many wafers having photo mask aligning errors will eventually lead to wafer scrapping. In order to improve the photo alignment signal (W.Q.) acquired from the relatively smaller 62um scribe-line's alignment mark while proceeding with the VIA layer photo aligning directly to its previous metal layer, it is found that removing the TiN hard mask (H.M.) just above the previous inter-metal dielectric (IMD) and alignment mark area can help the deep ultra-violet (DUV) 193nm wavelength ASML scanner stepper successfully acquires a better alignment signal and alignment accuracy (A.A.).However, due to copper (Cu) residues and CMP dishing after metal copper CMP, it has been found that both large area "half size open" and "full size open" approaches for TiN removing in the scribe-line alignment area can not be used. Hence, for safer photolithography aligning margin the "sizing + 0.25µm" mark on the scribe line's photo alignment area is suggested for better signal acquiring, whose experimental results in UMC shows that around 90% of the alignment signal (W.Q.) can be verified. The alignment accuracy (A.A.) can also be improved through using this technique and is accurate enough as compared to the conventional scanner alignment method used for above 0.13µm generation technology.

SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture. However, the success rate of defect detection, especially for soft single-column failures, is decreasing when traditional physical failure analysis (PFA) with only the bitmap is available for guidance. This is due to a variety of invisible or undetectable defects that cause leakage in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, a Conductive Atomic Force Microscope (C-AFM) [1-4] is introduced to perform junction-level fault isolation prior to attempting PFA. According to J. P. Morniroli [5], crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations to allow further characterization of these defects. In this study quantified data extracted using the C-AFM is also used to establish a connection between the failure mechanism discovered and the soft single column failure mode.

A 100Å-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully integrated with 14Å nitrided gate oxide as well as a 1200Å high-compressive PECVD ILD-SiN x stressing layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33% current gain. To achieve a poly-Si gate length target of 400Å (40nm), a 193nm scanner lithography and an aggressive oxide hard mask etching techniques were used. First, a 500Å-thick TEOS hard mask layer was deposited upon the 1500Å-thick poly-Si gate electrode. Second, both 1050Å-thick bottom anti-reflective coating (BARC) and 2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the plasma etcher's vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF (aq) solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of 40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching, which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14Å-thick nitrided gate oxide.

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