A thin FinFET Si-fin body structure fabricated with 193nm scanner photolithography and composite hard mask etching technique upon bulk-Si substrate

Liao, Wen‐Shiang; Liu, Yuhuan; Chang, Wen-Thong; Chen, Tung-Hung; Shih, Tommy; Tsen, Huan-Chiu; Chung, Lee

doi:10.1117/12.714391

Cited by 1 publication

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“…12,14,15 With CMOS device CDs being increasingly scaling down, the resist thickness must correspondingly be reduced to meet the requirements of lithography technology. 12,14,15 With CMOS device CDs being increasingly scaling down, the resist thickness must correspondingly be reduced to meet the requirements of lithography technology.…”

Section: Mechanism Analysis Causing Line Roughnessmentioning

confidence: 99%

Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure

Meng¹,

He²,

Li³

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the polysilicon gate etch based on the composite SiO 2 ∕Si 3 N 4 ∕SiO 2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO 2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon (α-Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.

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