A thick CESL stressed ultra-small (Lg=40nm) SiGe-channel MOSFET fabricated with 193nm scanner lithography and TEOS hard mask etching

Abstract

A 100Å-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully integrated with 14Å nitrided gate oxide as well as a 1200Å high-compressive PECVD ILD-SiN x stressing layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33% current gain. To achieve a poly-Si gate length target of 400Å (40nm), a 193nm scanner lithography and an aggressive oxide hard mask etching techniques were used. First, a 500Å-thick TEOS hard mask layer was deposited upon the 1500Å-thick poly-Si gate electrode. Second, both 1050Å-thick bottom anti-reflective coating (BARC) and 2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the plasma etcher's vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF (aq) solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of 40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching, which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14Å-thick nitrided gate oxide.