In the GE High-Density Interconnect Process, thermoplastic polyetherimide adhesives with selectively variable glass transition temperatures (Tg's) are used as chip attach and overlay adhesive. Alternating layers of patterned metal and dielectric are then applied to fabricate the interconnect structure. Upper layer dielectrics are formed using a modified siloxane-polyimide that can be processed at temperatures below 200 °C. The unique materials requirements and materials development issues associated with this approach are discussed.
In this paper, we show state of the art, low on-resistance, 25mW/1.2kV and 43mW/2.5kV SiC MOSFETs with excellent design robustness and process control such that the parametric spread of key device characteristics are approaching Si products. The impact of starting material variability on device performance is shown and design sensitivity curves are presented.
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