Abstract-This paper is devoted on the characterization method of RF/digital PCB interconnections for the prediction of the highspeed signal transient responses. The introduced method is based on the use of the interconnection line RLCG-model. Theoretical formulae enabling the extraction of the electrical per-unit length parameters R, L, C and G in function of the interconnection line physical characteristics (width, length, metal conductivity, dielectric permittivity . . . ) are established. Then, by considering the second order approximation of the interconnection RLCG-model transfer matrix, the calculation process of the transient responses from the interconnection system transfer function is originally established. To demonstrate the relevance of the proposed model, microwavedigital interconnection structure comprised of millimetre microstrip line driven and loaded by logic gates which are respectively modelled by their input and output impedances was considered. Then, comparisons between the SPICE-computation results and those obtained from the proposed analytical model implemented in Matlab were made. As results, by considering a periodical square microwave-digital excitation signal with 2 Gbits/s rate, transient responses which are very wellcorrelated to the SPICE-results and showing the degradation of the tested signal fidelity are observed. The numerical computations confirm that the proposed modelling method enables also to evaluate accurately the transient signal parameters as the rise-/fall-times and the 50% propagation delay in very less computation time. For this reason, this analytical-numerical modelling method is potentially interesting for the analysis of the signal integrity which propagates

This paper is devoted to the extension of the interconnect effect equalization concept with NGD circuits for UWB applications. First, RC interconnect effects are considered. It was found that by cascading with the NGD structure, the propagation delay of the considered rate 4 Gbps signal was compensated for about 98-%. Then, the feasibility of the technique by taking into account the interconnection inductive effect with RLC-model is also investigated. It was demonstrated that the technique proposed brings opportunities to compensate for simultaneously the propagation delay and distortions. Then, the application of the proposed technique for the optical interconnect correction is discussed.

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The H-tree interconnect network is frequently used for the clock signal sharing in the microelectronic systems. Due to the increase of complexity and operating processing data speed, these interconnect effects can bottleneck the technological advancement. Hence, more accurate interconnect modelling methods are necessary for electronic designers. For this reason, a simple and accurate ultra-wide band (UWB) model of multilevel distributed interconnection clock trees as a single input multiple outputs (SIMO) system is developed in this article. Very accurate single input single output (SISO) model transfer functions are derived. This method allows the signal integrity prediction regarding the distributed H-tree characteristics including the source and load impedances. In order to demonstrate the relevance of model developed, analyses of twoand three-level tree networks were performed. Distributed H-tree realistic devices formed by sub-millimetre physical length lines for applications for standardised Printed Circuit Board (PCB) interconnections were experimented numerically. The piece of lines constituting the trees is modelled by UWB RLCG network from DC to 8 GHz which takes into account the frequency dispersions and dielectric loss effects. Thus, excellent correlations between simulations and the results from the models proposed were observed both in frequency and time domains regarding 2.5 Gbits/s clock input.

SUMMARY This article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high‐speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.