Analysis of multi‐gigabits signal integrity through clock H‐tree

Abstract

The H-tree interconnect network is frequently used for the clock signal sharing in the microelectronic systems. Due to the increase of complexity and operating processing data speed, these interconnect effects can bottleneck the technological advancement. Hence, more accurate interconnect modelling methods are necessary for electronic designers. For this reason, a simple and accurate ultra-wide band (UWB) model of multilevel distributed interconnection clock trees as a single input multiple outputs (SIMO) system is developed in this article. Very accurate single input single output (SISO) model transfer functions are derived. This method allows the signal integrity prediction regarding the distributed H-tree characteristics including the source and load impedances. In order to demonstrate the relevance of model developed, analyses of twoand three-level tree networks were performed. Distributed H-tree realistic devices formed by sub-millimetre physical length lines for applications for standardised Printed Circuit Board (PCB) interconnections were experimented numerically. The piece of lines constituting the trees is modelled by UWB RLCG network from DC to 8 GHz which takes into account the frequency dispersions and dielectric loss effects. Thus, excellent correlations between simulations and the results from the models proposed were observed both in frequency and time domains regarding 2.5 Gbits/s clock input.

Kron‐Branin modeling of symmetric star tree interconnect

“…By taking: the output mesh is propagated by the current i o = i ok through the load resistance R and the Branin sources ( e k , e ok ) which are expressed as: …”

“…Nevertheless, it was found that the performance of certain clock tree topologies as H‐tree can be limited by the coupling and cross talk effects . So far, most of the developed analytical models of symmetric and asymmetric microstrip interconnect trees are using complex fastidious method using complex calculations of various parameters as Z, Y, and ABCD matrices . The complexity of the analytical calculations limits the model practicability.…”

UWB NGD circuit for time-delay reduction

“…With the increase of the electrical interconnect structures different phenomena linked to the EMI/EMC effects are occurred [1][2]. These unwanted effects can degrade significantly the operating signal integrity (SI).…”

“…These unwanted effects can degrade significantly the operating signal integrity (SI). So, modelling methods have been introduced which must be included during the design process have been developed [1][2].…”

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

“…Hence, floorplanning [1][2][3][4][5][6][7] is a crucial step in VLSI circuit design [8] as it determines the quality of the deep submicron chip quality, manufacturing cost and the time-to-market. Although there are several circuit design objectives to be considered during floorplanning, such as area minimization, wirelength optimization [9], delay reduction [10,11], thermal stability [12][13][14], clock tree synthesis [15] or any combination of these objectives [16][17][18], the basic objective of floorplanning is to minimize the area of the VLSI chip.…”