Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

Ravelo, Blaise; Eudes, Thomas

doi:10.1002/jnm.838

Cited by 11 publications

(10 citation statements)

References 24 publications

(40 reference statements)

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“…I point out that design and simulations of structures presented in this section were made in Schematic and Momentum environments of ADS software. By applying the RLCG modeling technique developed in [49][50][51], the per unit length parameters of each interconnect single line constituting the interconnect under test are R u = 74.6 Ω, L u = 9 nH and C u = 35 pF. By using these parameters, the formulation of the global reduced model established considered in Section 3 was applied by supposing that the IUT is loaded by parallel RC-network Z L = R L /C L .…”

Section: Description Of the Structure Under Testmentioning

confidence: 99%

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Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

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Abstract-An accurate and behavioral modeling method of symmetrical T-tree interconnect network is successfully investigated in this paper. The T-tree network topology understudy is consisted of elementary lumped L-cells formed by series impedance and parallel admittance. It is demonstrated how the input-output signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of L-cells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the T-tree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multi-level behavioral T-tree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of T-tree topology comprised of different and identical RLC-cells is conducted. To demonstrate the relevance of the model established, lumped RLC T-tree networks with different levels for the microelectronic interconnect application are designed and simulated. The work flow illustrating the guideline for the application of the routine algorithm summarizing the modeling method is proposed. Then, 3D-microstrip T-tree interconnects with width 0.1 µm and length 3 mm printed on FR4-substrate were considered. As results, a very good agreement between the results from the reduced behavioral model proposed and SPICE-computations is found both in frequency-and timedomains by considering arbitrary binary sequence "01001100" with 2 Gsym/s rate. The model proposed in this paper presents significant benefits in terms of flexibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this 24Ravelo work, the modeling of clock T-tree interconnects for packaging systems composed of distributed elements using an analogue process is in progress.

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Section: Description Of the Structure Under Testmentioning

confidence: 99%

“…With the increase of the circuit complexity, the interconnections are more and more complex as the case of tree networks [41][42][43][44][45][46][47][48]. But accurate and more relevant models are still needed for the multilevel T-tree interconnections as proposed in [51,52].…”

Section: Introductionmentioning

confidence: 99%

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

Self Cite

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“…First, by denoting f max , the maximal operating frequency and v, the speed of the signal propagating along the interconnect line, the rise-time of the input signal which must be higher than [15]:…”

Section: Extraction Of the Transient Response Parametersmentioning

confidence: 99%

“…Usually, the mathematical predictions enabling to model the undesired physical aspects (loss, distorsion, delay, overshoot…) induced by the interconnect structures are based on the electrical model defined by the per-unit length parameters RLCG [14][15][16]. Till now, the most popular theory used for the analytical investigations of the interconnect structure are based on the Elmore [17] and Wyatt [18][19][20] models named also as lumped RC-model are used by most industrial semi-conductor designers for estimating the typical linear system transient responses.…”

Section: Introductionmentioning

confidence: 99%

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Raveloa

2012

Eur. Phys. J. Appl. Phys.

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Abstract:A relevant modelling method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based-on the transfer matrix analysis, the second order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI parameters extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC-and RLC-lines excited by square-wave-pulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well-correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL parameters. Compared to other methods, the computation execution time and data-memory consumed by the program implementing the proposed delay modelling-method algorithm are much better.

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“…Consequently, the ABCD matrix is one parameter which allows one to explore this bottleneck [17], [29], particularly for estimating the transient responses [25][26][27][28]. This statement motivates us to develop simpler and faster models to forecast the transient responses for digital interconnection lines on PCBs to help designers for high-speed applications [13][14], [30]. Moreover, as exposed above, interconnects play an important role in designing modern electronic and microelectronic systems.…”

Section: Introductionmentioning

confidence: 99%

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

Eudes

Ravelo

Al-Hayek³

2013

AEM

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This paper is a special issue from the work presented in the Advanced Electromagnetics Symposium 2012 (AES'12) which presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/sinput data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

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Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

Cited by 11 publications

References 24 publications

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

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