Experimental studies of the etching of (Ba,Sr)TiO3 (BST) have been performed in Ar/halogen and Cl2 plasmas. In spite of the poor volatility of halogenated barium and strontium, some chemical enhancement of the etching reaction was observed in the etching of BST with halogen-containing plasmas. An investigation of the etching of BaOx, SrOx, TiOx, and BaxSryOz films with Cl2 plasma showed that the chemical enhancement in BST etching was related to the existence of titanium in BST films. The chemical reactivity of titanium with chlorine seemed to enhance the etching of BST. In the x-ray photoelectron spectroscopy analysis of the BST surfaces etched with Cl2 plasma, we found that barium- and strontium-rich surfaces were formed during the etching and that etching residues consisting of barium and strontium were observed after the BST films were etched off.
Etching yields of SiO2 by mass-separated F+, CF+, CF2+, CF3+, and Ar+ ions have been measured at low ion energies ranging from 80 to 350 eV. CF3+ and CF2+ ions have higher etching yields than CF+ and F+ ions. At low ion energies, SiO2 cannot be etched and some film deposition is observed on the SiO2 surface. For example, in the case of CF+ ions, SiO2 can be etched at ion energies above 200 eV. This film deposition is caused by reactions of CFx+ ions at the SiO2 surface, and neutrals coming from the ion source also have some effect on this deposition.
Great efforts have been made for the integration of high dielectric constant (Ba,Sr)Ti03 (BST) capacitors into DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs, with emphasis on key technical issues for process integration, including electrode materials, barrier layers, and also BST films themselves. The problems which may remain to be solved are also discussed to realize the goal: a barrier layer on top electrode for back-end processes, reliability of integrated BST capacitors, and further improvement of coverage properties of BST films and cell-plate metals.been achieved so far. On the other hand, in a 3-D stack, the sidewall capacitance increases with increasing the height of patterned stlorage nodes, which gives the scaling of this structure down to Gbit dimensions. These 3-D stack capacitors may be further classed under two types, having tapered and vertical storage nodes. It should be noted that for the 3-D stack with tapered storage nodes, their height is limited by geometrical conditions where the bottom of tapered electrodes would be buried in the small spacing between storage nodes; e.g., for a typical sidewall angle 8=70", the hleight of storage nodes is limited to D10.25 pm in 0.18 pm rule and to DI0.18 pm in 0.13 prn rule (4-Gbit), which in turn requires &,I0.34 nm and t&0.18 MI, respectively Introduction Electrode Materials From the technology perspective, the DRAM cell is rapidly shrinking as shown in Fig. 1, which in turn leads to aggressive scaling of memory cell capacitors while maintaining the storage capacitance therein.The minimum storage capacitance required remains to be C,225 @/cell even for Gbit-scale DRAMs, relying on the sense amplifier sensitivity, data retention time, and soft error immunity. Capacitor technology with high dielectric constant BST films has been developed to meet these requirements [ 1-51, as an alternative to capacitors using conventional dielectric materials such as Si3N4/SiOz and Taz05 which are now being actively studied in combination with HSG for 256-Mbit DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs and DRAM-embedded system LSIs, with emphasis on key technical issues for process integration such as electrode materials, barrier layers, and BST films themselves. The problems which may remain to be solved are also discussed to realize the goal.There are"a few different types of BST capacitor structures: a planar and a three-dimensional (3-0) stack capacitor, as shown in Table 1. The planar stack is scalable to 256-Mbit dimensions at most, as can be seen in Fig. 2, because the capacitance comes only from a planar dielectric layer between the bottom and top electrodes (i.e., storage node and cell plate). The equivalent oxide thickness required for a planar type (D=O) is around b=O.12 nm in 0.18 pm (1-Gbit) rule, which is far from the minimum %=0.24 nm that has The electrodle material for storage nodes is still the number one technical issue, because it g...
Experimental studies of the deposition of films formed on the sidewalls of a photoresist pattern in the etching of platinum films with Ar and halogen mixed gas plasmas were performed. In platinum etching with Ar/halogen gas plasmas there is no enhancement of the etch rate by adding halogen gases, and deposition films are formed on the sidewall of a photoresist pattern. The thickness of the sidewall deposition film is minimized in etching with pure Ar plasma. The addition of halogens increases the thickness of the sidewall deposition film. These films were analyzed by x-ray photoelectron spectroscopy ͑XPS͒ to investigate their formation mechanism. Carbon was detected even in the deposition films formed during etching with gases that did not include carbon. From the results of XPS analysis it was found that the etching reaction products from the photoresist relate to the formation of these films, and that the reason for the increase in the film thickness is the increase in the etch rate of the photoresist by adding halogens. Therefore in the etching of platinum films it is important to suppress the etching of the photoresist to decrease the thickness of the sidewall deposition film.
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