High efficiency cadmium sulfide (CdS)/cadmium telluride (CdTe) solar cells have been developed using ultrathin CdS films having a thickness of 50 nm. CdS films deposited on indium tin oxide (ITO)/#1737 glass substrates by the metal organic chemical vapor deposition technique, and CdTe films subsequently deposited by the close-spaced sublimation technique were used for the fabrication of CdS/CdTe solar cells. A photovoltaic conversion efficiency of 16.0% under Air Mass (AM) 1.5 conditions has been measured by the Japan Quality Assurance Organization.

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Cadmium sulfide (CdS) thin films are the most commonly used window materials for high efficient cadmium telluride (CdTe) and chalcopyrite polycrystalline thin-film photovoltaic devices. High efficient CdS/CdTe solar cells with thin CdS films have been developed using ultrathin CdS films with a thickness of less than 0.1 µm. CdS films were deposited on transparent conductive oxide (TCO)/glass substrates by the metal organic chemical vapor deposition (MOCVD) technique. CdTe films were subsequently deposited by the close-spaced sublimation (CSS) technique. The screen printing and sintering method fabricated carbon and silver electrodes. Cell performance depends primarily on the electrical and optical properties of CdS films. Therefore we started to develop higher-quality CdS films and found clear differences between high- and low-quality CdS films from the analyses of scanning electron microscope (SEM), atomic force microscope (AFM), secondary ion mass spectroscopy (SIMS), thermal desorption spectrometry (TDS) and Fourier transforms-infrared spectrometry (FT-IR) measurements. As a result of controlling the quality of CdS films, a photovoltaic conversion efficiency of 10.5% has been achieved for size of 1376 cm2 of the solar cells under the Air Mass (AM) 1.5 conditions of the Japan Quality Assurance Organization.

Drain current (ID) collapse-free i-GaN∕AlGaN∕GaN high-electron-mobility transistors (HEMTs) with and without surface passivation (electron-beam evaporated SiO2) were demonstrated using dc and pulsed (120Hz) IDS–VDS characteristics up to the drain supply voltage of 40V. The observation of small ID transients and negligibly small hysteresis widths with small white light illumination effects on both passivated and unpassivated i-GaN∕AlGaN∕GaN HEMTs confirms the suppression of collapse related traps. Three and two thermally activated trap levels were observed in passivated (+0.395, −0.079, and −0.949eV) and unpassivated (−0.066 and −0.368eV)AlGaN∕GaN HEMTs, respectively. However, i-GaN∕AlGaN∕GaN HEMTs with and without surface passivation exhibited only one trap level at −0.161eV. These results show that the addition of thin cap layer i-GaN screens the collapse-related surface states/traps from channel.

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