Damage-less full molecular-pore-stack SiOCH (MPS) / Cu interconnect is developed to reduce effective k-value (k eff ).MPS with high endurance against plasma processes is introduced into both via and trench dielectrics without hard mask (HM). Low friction slurry and chemical modification of MPS surface by He-plasma treatment suppress defect generation during direct CMP of the MPS surface. The full-MPS interconnect with low-k (k=3.1) cap demonstrates 10% lower inter-line capacitance and 34% lower inter-layer capacitance than the full-SiOCH (k=3.0) interconnect with SiCN-cap (k=4.9). The effective k-value k eff reduces to 2.67 for the damage-less full MPS structure which is applicable to 32nm LSIs and beyond.
Hybrid-type, Cu dual damascene interconnects (DDI) are fabricated in a porous organosilica film (k=2.1) inserted between low-k films of hard-mask (HM) and etch-stop (ES) layers, Plasma-polymerized, divinyl siloxane bisbenzocyclobutene @-BCB, k=2.7) film, instead of SiCN film (k>4), is selected for these HM and ES layers due to the low k-value as well as the high etch-stop property to the porous film. The line capacitance in the hybrid-type, Cu-DDI with BCB-HM and BCB-ES layers decreases 20% compared with that of the Cu-DDI with SO,-HM and SiCN-ES layers, achieving the effective dielectric constant (k.,J of 2.6. This new interconnect sttucture is a strong candidate for the 70nm-node ULSls.
Defectless monolithic low-k /Cu interconnects have been obtained for low-power LSIs by a chemically controlled local chemical mechanical polishing (CMP) process to remove a Cu/TaN barrier on hydrophobic SiOCH low-k films. In the first step, Cu-CMP, a unique end-pointdetection (EDP) method is implemented to detect a very thin Cu layer ($100 nm) that remains on the TaN barrier by in situ white-light interferometry, which is implemented in the local CMP apparatus where the wafers undergoing polishing are oriented face-up. In the second step, TaN-CMP, a SiO 2 hard-mask (HM) layer on the low-k film is selectively removed to reduce the nonuniformity of the Cu line thickness, and accordingly, those of the resistance and capacitance. Here, a CMP slurry with an oxidizer is used to change the low-k surface from a hydrophobic condition to a hydrophilic condition, improving wettability and reducing the number of scratches and abrasive particles. In the post-CMP cleaning, an alkaline rinse solution with an oxidation-reduction potential (ORP) of less than À0:5 V vs a normal hydrogen electrode (NHE) produces a clean low-k surface resulting in monolithic low-k /Cu interconnects with excellent dielectric properties comparable to those of SiO 2 /Cu interconnects.
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