High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32nm-node LSIs and beyond

Abstract

Damage-less full molecular-pore-stack SiOCH (MPS) / Cu interconnect is developed to reduce effective k-value (k eff ).MPS with high endurance against plasma processes is introduced into both via and trench dielectrics without hard mask (HM). Low friction slurry and chemical modification of MPS surface by He-plasma treatment suppress defect generation during direct CMP of the MPS surface. The full-MPS interconnect with low-k (k=3.1) cap demonstrates 10% lower inter-line capacitance and 34% lower inter-layer capacitance than the full-SiOCH (k=3.0) interconnect with SiCN-cap (k=4.9). The effective k-value k eff reduces to 2.67 for the damage-less full MPS structure which is applicable to 32nm LSIs and beyond.

Electrical Characteristics of Novel Non-porous Low-k Dielectric Fluorocarbon on Cu Interconnects for 22 nm Generation and Beyond

“…Variation of dielectric constant in a porous low-k film is known to be attributed by moisture uptake through pores and surface of the film conversion to hydrophilic due to the methyl group removal after dry etch process. 1,2,8) It is, however, noted that there is no pathway for water uptake due to non porous structure and hydrophobic surface remained after dry etch process in the fluorocarbon film. As a result, fluorocarbon film performed a remarkable robustness in terms of variation of dielectric constant.…”

“…Although porous low-k carbon-doped silicon oxide (SiCO:H) materials have been widely developed, challenges of process induced damage reduction are investigated. [1][2][3][4][5][6][7][8] Ishikawa et al reported that the influence of chemical mechanical polishing (CMP) on the degradation in leakage current and dielectric constant of porous low-k SiCO:H films. 2) Yoon et al reported that delamination or cracks of the SiCO:H films occurred during the CMP process because the adhesion between the porous low-k materials and other dielectrics was weak.…”

Challenges of 22 nm and beyond CMOS technology

“…7.4.2 Direct CMP. Ueki et al at NEC [177] reported in 2008 a full molecular-pore stacking (MPS) SiOCH (k=2.5) featured by small pore size (0.4 nm) and higher carbon content than other low K films with a similar k-value, and reported its high resistance against plasma process damage. To further reduce k eff , a two-layered full-MPS/Cu interconnect with silica-amorphouscarbon-composite (SACC) cap (k=3.1) is integrated by using direct CMP technique for MPS to as shown in Figure 7.7.…”

Improvement of Uniformity and Reliability of Scaled-Down Cu Interconnects with Carbon-Rich Low-k Films

“…For the 40 nm-node and beyond, low-k materials turn to be porous SiOCH of which k-values are less than 2.6. [1][2][3] The porous materials, however, suffer from the process induced damages in dry etching, metallization and chemical mechanical polishing (CMP). 1,[4][5][6][7] Especially, plasma induced damages (PID) in the dry etching process is widely studied by many groups.…”

“…[1][2][3] The porous materials, however, suffer from the process induced damages in dry etching, metallization and chemical mechanical polishing (CMP). 1,[4][5][6][7] Especially, plasma induced damages (PID) in the dry etching process is widely studied by many groups. [8][9][10] Since carbon depletion in the damaged layer raises k-value, Carbon (C)rich films are advantageous to suppress the plasma induced damages.…”