Damage-less full molecular-pore-stack SiOCH (MPS) / Cu interconnect is developed to reduce effective k-value (k eff ).MPS with high endurance against plasma processes is introduced into both via and trench dielectrics without hard mask (HM). Low friction slurry and chemical modification of MPS surface by He-plasma treatment suppress defect generation during direct CMP of the MPS surface. The full-MPS interconnect with low-k (k=3.1) cap demonstrates 10% lower inter-line capacitance and 34% lower inter-layer capacitance than the full-SiOCH (k=3.0) interconnect with SiCN-cap (k=4.9). The effective k-value k eff reduces to 2.67 for the damage-less full MPS structure which is applicable to 32nm LSIs and beyond.

A highly reliable, 65nm-node Cu interconnect technology has been developed with I 80nndZOOnm-pitched lines COnneCted through $IOOnm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-intra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the lineto-line TDDB reliability of the narrow-pitched Cu lines.The filly-scaled-down, 65nm-node Cu interconnects with the porous-on-rigidSiOCH hybrid structure achieve excellent performance and reliability.

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