A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

Tada, Munehiro; Harada, Y.; Tamura, Takashi; Inoue, N.; Ito, Fuminori; Yoshiki, M.; Ohtake, Hiroto; Narihiro, M.; Tagami, M.; Ueki, Makoto; Hijioka, K.; Abe, Mari; Takeuchi, T.; Saito, Shinobu; Onodera, Tsunenobu; Furutake, N.; Arai, Kazuo; Fujii, Ken; Hayashi, Y.

doi:10.1109/iedm.2003.1269411

Cited by 14 publications

(15 citation statements)

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“…The first pathway comprises interposing an additional layer between the ILD and the barrier layer. The deposition can be accomplished by CVD , or spin-on techniques, and the material can be organic , or inorganic , in nature. Of course, the inherent k -value of this material will have a direct effect on the overall dielectric constant, and for this reason, materials with relatively low dielectric constants are preferred.…”

Section: New Materials K < 22mentioning

confidence: 99%

Low Dielectric Constant Materials

2009

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Section: New Materials K < 22mentioning

confidence: 99%

Low Dielectric Constant Materials

2009

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“…Silicon carbides or nitrides, with k ranging from 4 to 5, are the commonly auditioned liners. [98][99][100] Silica-type liners with a lower k, such as SiO 2 (k∼4) 101,102 or plasma polymerized organic silica (referred to as DVS-BCB, k = 2.7) 103 have also been studied, but they were eventually discarded as their oxidizing deposition environment favors moisture uptake and their lower density leads to less efficient barrier properties. While it is relatively easy to deposit thin liners on low porosity dielectric materials, especially by ALD, it becomes a lot more challenging when the pore size is on the same order or bigger than the precursor molecules.…”

Section: Ecs Journal Of Solid State Science and Technology 4 (1) N30mentioning

confidence: 99%

Toward Successful Integration of Porous Low-k Materials: Strategies Addressing Plasma Damage

Lionti

Volksen

Magbitang

et al. 2014

ECS J. Solid State Sci. Technol.

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The increasing sensitivity of porous low dielectric constant materials to process damage constitutes a major roadblock to their implementation in back-end-of-the-line (BEOL) wiring structures for advanced technology nodes. In the early 2000s and in anticipation to future low-k related integration challenges, the semiconductor industry started to investigate the possibility to repair or prevent this damage. It is remarkable that the most disruptive solutions proposed today are inspired from the work initiated more than 10 years ago. In this review we first describe the accepted mechanisms for plasma damage, followed by a quick summary of the methods used to quantify its extent on both blanket films and patterned structures. We then report on the past and current strategies developed to mitigate the plasma damage of porous, low-k materials during damascene integration processes.

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“…Similarly, contact resistance was extrapolated from experimental data on 100 nm and larger via diameters and resulted in 18.5 for each metal contact as shown in Fig. 14 [48]- [51]. The estimations on contact resistance and wire resistivity likely contain errors since these parameters are extracted either from a technology that supports 100 nm wire features or extrapolated from a simplified scattering model that does not take account crucial scattering mechanisms such as interface (wire surface) and grain boundary scattering [52].…”

Section: A Parasitic Extraction and Postlayout Issuesmentioning

confidence: 99%

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit OFF currents under 1 pA while producing highest ON currents. DC characteristics of the optimum and -channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2-and 3-input NAND, NOR, and XOR gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 m 2 .Index Terms-Low-power very large scale integration (VLSI), metal-gate transistors, nanowire transistors, vertical silicon transistors.

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A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

Cited by 14 publications

References 0 publications

Low Dielectric Constant Materials

Low Dielectric Constant Materials

Toward Successful Integration of Porous Low-k Materials: Strategies Addressing Plasma Damage

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

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