Chip packaging technology with circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55) /Cu dual-damascene interconnects.Wire bonding damage is mainly improved by the pad structure. For molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65nm-node, ULSI chips are fumished in low-cost QFP with a conventional wire bonding.
The two‐step thermal anneal has been investigated in detail for the control of oxygen precipitation. The correlations of interstitial oxygen reduction after the two‐step thermal anneal, the interstitial oxygen in the as‐grown wafer, and the microdefect density are made clear. There is a critical oxygen concentration for the oxygen precipitation. It depends on the first step annealing time and the substitutional carbon concentration. The two‐step thermal anneal was applied successfully to a CCD image sensor and CMOS LSI to improve their performance.
We establish hydrodynamic equations which describe the shear dynamics of a supercooled liquid composed of anisotropic molecules. We use these equations to analyse 90 • depolarized light scattering experiments performed in supercooled metatoluidine, and show that the shear viscosity values extracted from the analysis are consistent with independent static measurements performed in the same temperature range. 0953-8984/99/SA0139+08$19.50
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