Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Tada, Munehiro; Tamura, T.; Ito, Fuminori; Ohtake, Hiroto; Narihiro, M.; Tsuji, Masayoshi; Ueki, Makoto; Hijioka, K.; Abe, Mari; Inoue, N.; Takeuchi, T.; Saito, Shinobu; Onodera, T.; Furutake, N.; Arai, Ken‐ichi; Sekine, Makoto; Suzuki, Masahiro; Hayashi, Y.

doi:10.1109/ted.2006.872095

Cited by 15 publications

(13 citation statements)

References 23 publications

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“…In light of these developments, it has been pointed out that interconnect LER increases resistivity and degrades time-dependent dielectric breakdown (TDDB) immunity. [9][10][11][12][13] The latter problem was actually observed. 11) Degradation of TDDB immunity, which is particularly serious in Cu/low-k interconnects (for example refs.…”

Section: Introductionmentioning

confidence: 78%

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Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

Yamaguchi¹,

Ryuzaki²,

Takeda³

et al. 2008

jjap

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To establish a method of measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric field concentration was simulated on the basis of observation results. Wedge-shaped LERs were observed at the edges of low-k lines, and the bottom and the top widths of the average wedge feature were 60 and 7 nm (or smaller), respectively. Simulation showed that LER causes serious electric field concentration, which may cause the degradation of time-dependent dielectric breakdown (TDDB) lifetime at 100-nm-pitch Cu/low-k interconnects. The maximum electric field strength depends on the conventional LER metric 3R q , but depends more strongly on the wedge angle, the curvature of the tip. That is, other metrics such as wedge angle can predict fatal electric field concentration caused by LER than the conventional metric 3R q .

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Section: Introductionmentioning

confidence: 78%

“…11) Degradation of TDDB immunity, which is particularly serious in Cu/low-k interconnects (for example refs. [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19], is caused by a wedge-shaped LER, as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

Yamaguchi¹,

Ryuzaki²,

Takeda³

et al. 2008

jjap

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“…Deposition of thin, continuous metal barrier layers (such as TaN/Ta) is more difficult as pore size increases; incomplete barrier coverage can result in Cu diffusion into the dielectric [26]. A number of dielectrics have been examined as pore sealing materials including SiCH, SiOC, SiO 2 [90], and divinyl-siloxane benzocyclobutene polymer (p-BCB) [89]. Hence, even for well-designed porous low-k materials (i.e., with isolated pores less than 2 nm in diameter), the metal thickness is approaching the pore size.…”

Section: Metallizationmentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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“…Since the problem of electric field concentration is the same as discussed for the interconnect layer [13][14][15][16][17], we initially wanted to look at the best method for identifying the areas on a spoked structure with the largest E-field strength by simulations. The simulations were used to create a set of criteria that identify problem spots in samples via critical dimension scanning electron microscope metrology.…”

Section: Introductionmentioning

confidence: 99%

“…With typical post develop CD's ranging from 40-60 nm in the 22 nm node and even smaller in the 16 nm node, ER on the order of 10% can drastically impact final device performance or reliability and is not a negligible [1,2]. Most of the recent work in studying how ER is related to performance or reliability has focused on looking at the impact of line edge roughness (LER) in the gate and interconnect levels [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17].With such intense scrutiny on LER, some have also begun studying contact edge roughness (CER) and its impact on the contact and via levels [1,2]. Both LER and CER are caused by process variation by intrinsic imaging properties of the resist coupled with image contrast [18], and although both can be minimized, CER tends to be more random in occurrence then LER.…”

mentioning

confidence: 99%

CD-SEM metrology of spike detection on sub-40 nm contact holes

et al. 2010

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In this work, for the purpose of contact-hole process control, new metrics for contact-hole edge roughness (CER) are being proposed. The metrics are correlated to lithographic process variation which result in increased electric fields; a primary driver of time-dependent dielectric breakdown (TDDB). Electric field strength at the tip of spokeshaped CER has been simulated; and new hole-feature metrics have been introduced. An algorithm for defining critical features like spoke angle, spoke length, etc has been defined. In addition, a method for identifying at-risk holes has been demonstrated. The number of spike holes can determine slight defocus conditions that are not detected though the conventional CER metrics. The newly proposed metrics can identify contact holes with a propensity for increased electric field concentration and are expected to improve contact-hole reliability in the sub-40-nm contact-hole process. INTRODUCTIONLSI devices continue to shrink in size and increase in fabrication complexity. As the number of process variables increase, yield has become an ever challenging criteria to meet. One of the contributing factors that have been of an increasing focus is edge roughness (ER). With typical post develop CD's ranging from 40-60 nm in the 22 nm node and even smaller in the 16 nm node, ER on the order of 10% can drastically impact final device performance or reliability and is not a negligible [1,2]. Most of the recent work in studying how ER is related to performance or reliability has focused on looking at the impact of line edge roughness (LER) in the gate and interconnect levels [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17].With such intense scrutiny on LER, some have also begun studying contact edge roughness (CER) and its impact on the contact and via levels [1,2]. Both LER and CER are caused by process variation by intrinsic imaging properties of the resist coupled with image contrast [18], and although both can be minimized, CER tends to be more random in occurrence then LER. An additional complication with CER is in the definition the edge roughness itself. There are two common definitions of this ER mechanism. The first is the deviation of the processed structure from that of a perfect circle, or its ellipticity. The second definition is related to the first in that it is a metric of circularity, but more focuses on the presence of a concave or convex protrusions in the hole structure. It is this second definition that is critical to device reliability as it can cause either enhancements in the electric field or shorting in a device; and not only a degradation in the time dependant dielectric breakdown (TDDB) but a loss of yield [2].In light of the above-described circumstances, new CER metrics are proposed to identify the number of these spoked holes for process control and optimization. Since the problem of electric field concentration is the same as discussed for the interconnect layer [13-17], we initially wanted to look at the best method for identifying the areas on a spoke...

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Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Cited by 15 publications

References 23 publications

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

Process Technology for Copper Interconnects

CD-SEM metrology of spike detection on sub-40 nm contact holes

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