Process Technology for Copper Interconnects

Gambino, J.

doi:10.1016/b978-1-4377-7873-1.00008-5

Cited by 15 publications

(10 citation statements)

References 160 publications

(238 reference statements)

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“…ALD is a technique for producing highly conformal thin lms, and lms deposited by ALD are very relevant to semiconductor manufacturing. [21][22][23][24] Each ALD cycle here consists of the appropriate two half reactions. These surfaces were cleaned with atomic oxygen prior to analysis, and therefore the outermost layer of the material is expected to be fully oxidized.…”

Section: Overviewmentioning

confidence: 99%

“…53 The target for diffusion barrier layer thickness at the 22 nm node is 3 nm. 21 This downward trend in lm thicknesses will probably continue as technology advances to the 10 nm and 7 nm nodes. In short, as lms get thinner, surface sensitivity will become increasingly important for understanding lm properties in semiconductors.…”

Section: Application Of Leis To Semiconductors 39mentioning

confidence: 99%

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Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

et al. 2016

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Section: Overviewmentioning

confidence: 99%

Section: Application Of Leis To Semiconductors 39mentioning

confidence: 99%

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

et al. 2016

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“…Currently, there are two main approaches to reduce the Ä value of dielectric films: material composition modification and porosity introduction. For silica-based low-Ä dielectrics, replacing part of the Si-O bond with C-C and C-F bonds can reduce the polarity of the molecule structure, thus reducing the Ä value, such as SiBCN, SiOCN, SiCOH, and fluorosilicate glass (FSG) [45] . Because air or vacuum has the lowest dielectric constant (Ä = 1), it is the ideal gate spacer or intra-metal dielectric for reducing parasitic capacitance in future technology nodes.…”

Section: Technical Specificationmentioning

confidence: 99%

Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore's law will undoubtedly continue in the next 15 years.

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“…The first task is to incorporate copper into the system. The IC industries replaced aluminum wiring with a lower resistance copper to minimize the resistance-capacitance (RC) delay of transistors [54,55]. The replacement of aluminum introduced more complications on the damascene process because copper is not suitable for reactive ion etching due to the low volatile by-products that can diffuse into the pores from the ILDs.…”

Section: Dual-damascene Process and Plasma-induced Damagementioning

confidence: 99%

The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

et al. 2021

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Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

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Process Technology for Copper Interconnects

Cited by 15 publications

References 160 publications

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

Low energy ion scattering (LEIS). A practical introduction to its theory, instrumentation, and applications

Advanced process and electron device technology

The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

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