CD-SEM metrology of spike detection on sub-40 nm contact holes

Abstract

In this work, for the purpose of contact-hole process control, new metrics for contact-hole edge roughness (CER) are being proposed. The metrics are correlated to lithographic process variation which result in increased electric fields; a primary driver of time-dependent dielectric breakdown (TDDB). Electric field strength at the tip of spokeshaped CER has been simulated; and new hole-feature metrics have been introduced. An algorithm for defining critical features like spoke angle, spoke length, etc has been defined. In addition, a method for identifying at-risk holes has been demonstrated. The number of spike holes can determine slight defocus conditions that are not detected though the conventional CER metrics. The newly proposed metrics can identify contact holes with a propensity for increased electric field concentration and are expected to improve contact-hole reliability in the sub-40-nm contact-hole process. INTRODUCTIONLSI devices continue to shrink in size and increase in fabrication complexity. As the number of process variables increase, yield has become an ever challenging criteria to meet. One of the contributing factors that have been of an increasing focus is edge roughness (ER). With typical post develop CD's ranging from 40-60 nm in the 22 nm node and even smaller in the 16 nm node, ER on the order of 10% can drastically impact final device performance or reliability and is not a negligible [1,2]. Most of the recent work in studying how ER is related to performance or reliability has focused on looking at the impact of line edge roughness (LER) in the gate and interconnect levels [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17].With such intense scrutiny on LER, some have also begun studying contact edge roughness (CER) and its impact on the contact and via levels [1,2]. Both LER and CER are caused by process variation by intrinsic imaging properties of the resist coupled with image contrast [18], and although both can be minimized, CER tends to be more random in occurrence then LER. An additional complication with CER is in the definition the edge roughness itself. There are two common definitions of this ER mechanism. The first is the deviation of the processed structure from that of a perfect circle, or its ellipticity. The second definition is related to the first in that it is a metric of circularity, but more focuses on the presence of a concave or convex protrusions in the hole structure. It is this second definition that is critical to device reliability as it can cause either enhancements in the electric field or shorting in a device; and not only a degradation in the time dependant dielectric breakdown (TDDB) but a loss of yield [2].In light of the above-described circumstances, new CER metrics are proposed to identify the number of these spoked holes for process control and optimization. Since the problem of electric field concentration is the same as discussed for the interconnect layer [13-17], we initially wanted to look at the best method for identifying the areas on a spoke...

Contact edge roughness (CER) characterization and modeling: effects of dose on CER and critical dimension (CD) variation

“…Regarding CER, one can find in literature few papers which use conventional AFM for the characterization of the sidewall roughness of photonic crystal holes [5], while no work has been done on scatterometry. In this work, we follow the main trend and use top-down SEM images as input in CER evaluation methodology [1][2][3][6][7][8][9]. The steps of this methodology are shown schematically in Fig.…”

“…Although both LER and CER refer to the deviation of real pattern edges from ideal smooth ones, one can notice some differences: 1) The first difference has to do with the degradation effects they cause on device performance. LER/LWR affects mainly the threshold voltage for transistor operation and the transistor-off leakage current, whereas CER has been shown to cause time-dependent dielectric breakdown (TDDB) due to the reduction of the space between contact and gate in a transistor, affect the Source/Drain (S/D) contact resistance and the saturation current, and furthermore change the refractive index of photonic crystal holes [1][2][3]. The TDDB effect has inspired a characterization approach to CER different than that of LER based on the identification and characterization of protruding spikes in contact edge [2].…”

“…LER/LWR affects mainly the threshold voltage for transistor operation and the transistor-off leakage current, whereas CER has been shown to cause time-dependent dielectric breakdown (TDDB) due to the reduction of the space between contact and gate in a transistor, affect the Source/Drain (S/D) contact resistance and the saturation current, and furthermore change the refractive index of photonic crystal holes [1][2][3]. The TDDB effect has inspired a characterization approach to CER different than that of LER based on the identification and characterization of protruding spikes in contact edge [2]. 2) The second set of differences is related to the different topology of CER with respect to LER and its metrological implications.…”

Contact edge roughness and CD uniformity in EUV: effect of photo acid generator and sensitizer

“…Besides this, roughness may appear at the sidewalls of contacts in transistors which is usually called Contact Edge Roughness (CER). CER have various effects on device performance, the first effect has to do with time-dependent dielectric breakdown (TDDB) [3]. This is due to the reduction of the space between contact and gate in a transistor because of CER.…”

Critical dimension uniformity and contact edge roughness in extreme ultraviolet lithography: effect of photoacid generator, sensitizer and quencher

“…[2][3][4][5][6][7] Furthermore, the sidewall roughness of single contacts [usually called contact edge roughness (CER)] has various effects on transistor performance such as the time-dependent dielectric breakdown coming from the reduction of the space between the contacts and gate in a transistor and the saturation value of source/drain current. 11 The increased importance of contact roughness and variability issues demands first for a reliable and advanced measurement and characterization approach [8][9][10][11][12][13] and second, for systematic experimental and modeling studies investigating the CD variation and CER dependencies on various EUV resist properties and process conditions. 11 The increased importance of contact roughness and variability issues demands first for a reliable and advanced measurement and characterization approach [8][9][10][11][12][13] and second, for systematic experimental and modeling studies investigating the CD variation and CER dependencies on various EUV resist properties and process conditions.…”