A 0.3Spm CMOS process for low-voltage, highperformance ASIC's, implemented on ultra-thin SO1 (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1 . 5~ are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1 . 5~ supply voltage, demonstrating the excellent performance of this technology.
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