Channel-drain lateral profile engineering for advanced CMOS on ultra-thin SOI technology

Adan, A.O.; Kaneko, Shinji; Naka, T.; Urabe, D.; Higashi, K.; Kagisawa, A.

doi:10.1109/soi.1996.552513

Cited by 4 publications

(2 citation statements)

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“…Reduction of the Short-Channel Effects (SCE) are a concern in low-Vth transistors. In this technology excellent SCE performance were obtained by optimization of the channel-drain lateral profile engineering [5].The N and PMOS Vth CJ are 20mV and 17mV, respectively, for the nominal 0.35pm gate length transistors.…”

Section: Device Designmentioning

confidence: 98%

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Low-voltage 0.35 μm CMOS/SOI technology for high-performance ASIC's

Adan¹,

Naka²,

Kaneko³

et al.

Proceedings of CICC 97 - Custom Integrated Circuits Conference

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A 0.3Spm CMOS process for low-voltage, highperformance ASIC's, implemented on ultra-thin SO1 (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1 . 5~ are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1 . 5~ supply voltage, demonstrating the excellent performance of this technology.

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Section: Device Designmentioning

confidence: 98%

“…A key consideration in the design of portable electronic equipments is to maintain high performance at low-voltage operation (Vdd-1. 5) .…”

Section: Introductionmentioning

confidence: 99%