Device integration of a 0.35 μm CMOS on shallow SIMOX technology for high-speed and low-power applications

Adan, A.O.; Naka, T.; Kaneko, Shinji; Urabe, D.; Higashi, K.; Kagisawa, A.

doi:10.1109/soi.1996.552521

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Cited by 3 publications

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“…A cross-section schematic of the CMOS on SO1 devices is given in Fig.1 [3]. The starting substrate is a low oxygen dose SIMOX (Separation by Implantation of Oxygen) wafer with a buried oxide layer 100 nm thick.…”

Section: Process Flowmentioning

confidence: 99%

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Low-voltage 0.35 μm CMOS/SOI technology for high-performance ASIC's

Adan¹,

Naka²,

Kaneko³

et al.

Proceedings of CICC 97 - Custom Integrated Circuits Conference

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A 0.3Spm CMOS process for low-voltage, highperformance ASIC's, implemented on ultra-thin SO1 (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1 . 5~ are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1 . 5~ supply voltage, demonstrating the excellent performance of this technology.

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Section: Process Flowmentioning

confidence: 99%

“…The electrostatic discharge (ESD) strength performance of this 0.35pm SO1 technology is illustrated in Fig.10. Lateral punchthrough devices, inherent in the SIMOX process [3], allowed to achieve 4 kV and 300 V ESD strength for the Human Body and the Machine Model stress conditions, respectively.…”

Section: Device Characteristicsmentioning

confidence: 99%