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This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements.Index Terms-Circuit simulation, error correction, fault injection, sequential element design, soft error rate (SER).

We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D)

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This paper presents an overview of the Built-In Soft Error Resilience (BISER) technique for correcting soft errors in latches, flip-flops and combinational logic. The BISER technique enables more than an order of magnitude reduction in chip-level soft error rate with minimal area impact, 7-11% chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several classical error-detection techniques introduce 40-100% power, performance and area overheads, and require significant efforts in designing and validating corresponding recovery mechanisms. Design trade-offs associated with the BISER technique and other existing soft error protection techniques are also analyzed. 1 Who Cares about Soft Errors? only a major concern for space applications. That scenario has changed. Terrestrial radiation has been a growing concern, and many designs today implement extensive error SRAMs. However, memory protection alone is not enough for designs in sub-65nm technologies. Most future designs targeting enterprise computing and communication to be 10 FIT, where 1 FIT corresponds to one error per billion device hours. According to recent Errors Workshop, www.selse.org), a typical value for latch soft error rate may be assumed of design hierarchy and manufacturing process. The soft error rate of a design is generally quantified in terms of Failure-in-time, or Soft errors are radiation-induced transient errors caused by neutrons generated from detection and correction by way of Error Correcting Codes (ECC) mainly for on-chip-3 cosmic rays and alpha particles from packaging material. Traditionally, soft errors were FIT. Note that, there is a lot of variance in latch soft error rates depending on SRAMs. While combinational logic protection may not be an immediate necessity, it may Please use the following format when citing this chapter: There are multiple ways to minimize system-level soft error rate, applied at various levels eventually be required as more and more transistors are integrated in future technologies.

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