Defect and error tolerance in the presence of massive numbers of defects

Breuer, M.A.; Gupta, Sandeep; Mak, T.M.

doi:10.1109/mdt.2004.8

Cited by 189 publications

(85 citation statements)

References 4 publications

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“…This increase in distortion (ESAD) may lead to a rate increase (∆R) for a given QP . For 1 Note that this could be replaced by another selection metric, e.g., one involving a Lagrangian cost.…”

Section: Motion Estimation With Multiple Imprecise Computationsmentioning

confidence: 99%

“…(ET), which has been considered in more general settings, including hard hardware faults [1]. Our previous work has demonstrated that image/video compression systems exhibit ET characteristics, even if no explicit error control block is added in the presence of VOS [2] (additional work dealing with hard errors due to deterministic faults shows similar results [7,5]).…”

Section: Introductionmentioning

confidence: 99%

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Power Efficient Motion Estimation using Multiple Imprecise Metric Computations

Chong

Ortega

2007

Multimedia and Expo, 2007 IEEE International Conference On

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In this paper, we propose power efficient motion estimation (ME) using multiple imprecise sum absolute difference (SAD) metric computations. We extend recent work in [18] by providing analytical solutions based on modelling of computation errors due to voltage over scaling (VOS) and sub-sampling (SS). Results show that our solutions provide significantly better performance in the sense of rate increase for fixed QP , e.g., less than 5% increase, while in [18] the rate increase could be as high as 20%. Our analysis also allows us to compare different ME algorithms (e.g., full search vs. a fast algorithm) and SAD computation architectures (parallel vs. serial) in terms of their robustness to imprecise metric computations and their power efficiency. Finally, we demonstrate that additional power savings can be achieved by removing redundancy between the various computations.

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Section: Motion Estimation With Multiple Imprecise Computationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Power Efficient Motion Estimation using Multiple Imprecise Metric Computations

Chong

Ortega

2007

Multimedia and Expo, 2007 IEEE International Conference On

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“…During all these years both stages have had an independent and isolated evolution one of the other [3] . This separation has been an additional benefit for the semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

“…Such small dimensions imply that we are leaving the statistical bulk principles and entering in a behaviour related with discrete amounts of atoms. This causes a loss of control in the manufacturing process [3] and a consequent drop in the manufacturing yield becoming a critical situation for the further evolution of semiconductor technology. …”

Section: Introductionmentioning

confidence: 99%

Desigining Circuits from Imperfect Components in VISI Giga-scale Technologies

Rubio

Martorell

Moll

2006

Int. J. Soc. Mater. Eng. Resour

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The evolution of the integrated circuit technology during the last 3 decades has been based on an increasing accuracy of the manufacturing process. With this principle and by using a quality control at the end of the production line (Test Technology) the semiconductor industry has reached very high productivity levels. However, with technology reaching critical sizes ( < 65 nm) the manufacturing control is starting to fail and new design principles have to be introduced to be able to produce functional chips from low quality components. In this article two scenarios partially addressing the problem with gradual introduction of redundancy are considered: the scenario of the era at the end of the CMOS Moore's Law and the expected next scenario of nanoelectronic technology using new emergent devices. In the paper techniques for the design of robust electronic systems in spite of the low quality of components are presented for the two scenarios.

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“…Similarly, routers can fail as any processor implemented on chip. Moreover, an increase in the number of transistors on-chip would result in more transient and permanent failures of signals, logic values and interconnects [11], [12], [13]. Although already available standard diagnosis and fault tolerance test may be applied to NoCs, yet they don't exploit any particular network properties.…”

Section: Network On Chips (Noc)mentioning

confidence: 99%