Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors

Metra, C.; Omaña, M.; Mak, T.M.; Rahman, Akond; Tam, Simon

doi:10.1109/dft.2008.51

Cited by 6 publications

(23 citation statements)

References 17 publications

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“…As for clock jitter measurement, we follow the usual approach of measuring the duration of the clock high or/and low phase/s over time, and comparing them to their expected duration for the case of jitter-free clock [9]. For the sake of brevity, we will here consider the case of the clock high phase measurement only, which can however be extended to both clock phases by straightforward modifications.…”

Section: Proposed On-die Measurement Schemementioning

confidence: 99%

“…Since the global delay of the NOT chain used for jitter measurements should be long enough to cover the whole clock period (T CK ) [9], we re-used a number k of NOTs of the RO, such that kτ > T CK (Figure 2(a)). With respect to the scheme in Figure 1, we connected a multiplexer (M1 in Figure 2(a)) to the input of the N1 NAND.…”

Section: Proposed On-die Measurement Schemementioning

confidence: 99%

“…In Section IV, we show some of the results of the electrical level simulations performed to verify its accuracy in measuring clock jitter and process parameter variations. In Section V, we evaluate the costs of our proposed scheme and compare them to those of the schemes in [10] and [9] to measure process parameter variations and clock jitter, respectively. Finally, in Section VI, we draw some conclusive remarks.…”

Section: Introductionmentioning

confidence: 99%

“…In order to cope with these problems, several measurement schemes have been proposed for clock jitter (e.g., those in [4][5][6][7][8][9]) and process parameter variations ( [10][11][12]), these latter generally all based on the use of Ring Oscillators (ROs).…”

Section: Introductionmentioning

confidence: 99%

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On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

Omaña

Giaffreda

Metra

et al. 2010

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

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We present a novel low cost scheme for the on-die measurement of either clock jitter, or process parameter variations. By re-using and properly modifying the Ring Oscillators (ROs) that are currently widely employed for process parameter variation measurement in high performance microprocessors, our proposed scheme can be easily set in either the process parameter variation measurement mode, or the clock jitter measurement mode, by acting on an external control signal. This way, during the test or debug phase, clock jitter can also be measured at negligible area and power costs with respect to process parameter variation measurement only. Our scheme is scalable in the provided clock jitter measurement resolution, while allowing the same process parameter variation measurement resolution as the currently employed RO based schemes. Moreover, due to its allowing both process parameter variation and clock jitter measurements, our scheme features accurate clock jitter measurement despite the possible presence of significant process parameter variations.keywords -process parameter variations; clock jitter; measurement scheme; high performance microprocessor.

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Section: Proposed On-die Measurement Schemementioning

confidence: 99%

Section: Proposed On-die Measurement Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

Omaña

Giaffreda

Metra

et al. 2010

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

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show abstract

“…Based on the limitations of the approaches proposed so far to achieve high jitter measurement resolution and accuracy at limited costs, in this paper we present a new on-chip digital measurement scheme, whose basic structure has been introduced in [18]. It allows to measure clock jitter with high and scalable resolution at limited costs, and with high accuracy despite the presence of PSN.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost On-Chip Clock Jitter Measurement Scheme

Omaña

Rossi

Giaffreda

et al. 2015

IEEE Trans. VLSI Syst.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk TVLSI-00144-2013 1  Abstract-In this paper we present a low cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in-situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing Ring Oscillators (ROs) to measure process parameter variations, our jitter measurement scheme can be implemented by re-using part of such ROs, thus allowing to measure clock jitter with very limited cost increase compared to process parameter variation measurement only, and with no impact on parameter variation measurement resolution.

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Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip

Guang

Nigussie

Tenhunen

2010

23rd IEEE International SOC Conference

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System-level exploration of a novel Network-on Chip (NoC) architecture with run-time communication bypass ing is presented. Fine-grained DVFS (Dynamic Voltage and Frequency Scaling) is an effective power reduction technique. We propose run-time reconfigurable interconnect on each inter router channel to minimize the latency and energy overhead. When two routers are running on the same frequency, FIFO channel is bypassed by direct interconnect. Distributed algorithm is designed for per-core DVFS. Proper power delivery and clocking scheme are integrated. Simulation shows significant energy and latency saving.

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Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors

Cited by 6 publications

References 17 publications

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

Low-Cost On-Chip Clock Jitter Measurement Scheme

Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip

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