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This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements.Index Terms-Circuit simulation, error correction, fault injection, sequential element design, soft error rate (SER).

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In this work we present a-particle induced soft error rates (SER) for several generations of the Alpha microprocessor. In our analysis we particularly focus on the historical trend of soft error rates for memory cells and random core logic. Our data demonstrate the impact of process, design and packaging material on the SER. The total chip-level SER trend has not been monotonic over the last couple of process generations, whereas the susceptibility to aparticle induced soft errors has actually decreased for both the core logic and memory cells. For all investigated technologies, the core SER is dominated by asynchronous as opposed to synchronous soft errors. [