Decimal multiplication is an integral part offinancial, commercial, and internet-based

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-In a sigma-delta analog to digital (A/D)As most of the sigma-delta ADC applications require converter, the most computationally intensive block is decimation filters with linear phase characteristics, the decimation filter and its hardware implementation symmetric Finite Impulse Response (FIR) filters are may require millions of transistors. Since these widely used for implementation. But the number of FIR converters are now targeted for a portable application, filter coefficients will be quite large for implementing a a hardware efficient design is an implicit requirement. narrow band decimation filter. Implementing decimation In this effect, this paper presents a computationally filter in several stages reduces the total number of filter efficient polyphase implementation of non-recursive coefficients, and hence reduces the hardware complexity cascaded integrator comb (CIC) decimators for and power consumption [2]. Sigma-Delta Converters (SDCs). The SDCs areThe first stage of decimation filter can be operating at high oversampling frequencies and hence implemented very efficiently using a cascade of integrators require large sampling rate conversions. The filtering and comb filters which do not require multiplication or and rate reduction are performed in several stages to coefficient storage. The remaining filtering is performed reduce hardware complexity and power dissipation. either in single stage or in two stages with more complex The CIC filters are widely adopted as the first stage of FIR or infinite impulse response (IIR) filters according to decimation due to its multiplier free structure. In this the requirements. The amount of passband aliasing or research, the performance of polyphase structure is imaging error can be brought within prescribed bounds by compared with the CICs using recursive and increasing the number of stages in the CIC filter. The non-recursive algorithms in terms of power, speed and width of the passband and the frequency characteristics area. This polyphase implementation offers high speed outside the passband are severely limited. So, CIC filters operation and low power consumption. The polyphase are used to make the transition between high and low implementation of 4th order CIC filter with a sampling rates. Conventional filters operating at low decimation factor of '64' and input word length of sampling rate are used to attain the required transition '4-bits' offers about 70% and 37% of power saving bandwidth and stopband attenuation. compared to the corresponding recursive and Several papers are available in literature that deals non-recursive implementations respectively. The same with different implementations of decimation filter polyphase CIC filter can operate about 7 times faster architecture for sigma-delta ADCs. Hogenauer has than the recursive and about 3.7 times faster than the described the design procedures for decimation and non-recursive CIC filters.interpolation CIC filters with emphasis on frequency response and register width [3]. A power efficien...

Active layer thickness variation in highly-doped amorphous indium-gallium-zinc oxide thin film transistors with molybdenum-chromium contacts is studied to reveal parametric dependencies under both channel length and gate-contact overlap length scaling. Devices with thickness variations from 5 nm to 30 nm, channel length variation from 3 µm to 100 µm and gate-contact overlap length variation from 1 µm to 10 µm were fabricated, characterized and analyzed. Analysis from a field effect transistor perspective show typical thickness variation trends where threshold voltage shifts positively, subthreshold slope improves and I on /I off ratio increases as the active layer thickness is scaled down. Peculiar observations like extremely low saturation voltage, insensitivity towards channel length variations, two different slopes in the subthreshold region and peaks in the transconductance characteristics can be explained only by invoking the principle of Schottky transistor operation. Thinner devices exhibit high field Schottky operation with barrier lowering which causes monotonously increasing transconductance, while thicker devices show low field behavior with no barrier lowering signified by peaks with saturated behavior of transconductance. Channel length modulates this dependence of transconductance on thickness. Sensitivity towards gate-contact overlap length scaling increases with thickness. Devices with active layer thickness of 5 nm can withstand overlap length scaling up to 5 µm without transconductance degradation, while devices of 10 nm thickness can withstand overlap length scaling only upto 10 µm. Devices of 30 nm thickness show contact limited operation even at 10 µm overlap length. Conventional FET operating principles cannot explain these observations and the phenomenon of Schottky contact transistor operation has been invoked. The results point towards a thin borderline in low dimensional transistors, differentiating a FET from Schottky contact transistors, through a field dependent barrier lowering mechanism, which is modulated by active layer thickness, channel length and gate contact overlap length.

The modern telecommunication industry demands higher capacity networks with high data rate. Orthogonal frequency division multiplexing (OFDM) is a promising technique for high data rate wireless communications at reasonable complexity in wireless channels. OFDM has been adopted for many types of wireless systems like wireless local area networks such as IEEE 802.11a, and digital audio/video broadcasting (DAB/DVB). The proposed research focuses on a concatenated coding scheme that improve the performance of OFDM based wireless communications. It uses a Redundant Residue Number System (RRNS) code as the outer code and a convolutional code as the inner code. The bit error rate (BER) performances of the proposed system under different channel conditions are investigated. These include the effect of additive white Gaussian noise (AWGN), multipath delay spread, peak power clipping and frame start synchronization error. The simulation results show that the proposed RRNS-Convolutional concatenated coding (RCCC) scheme provides significant improvement in the system performance by exploiting the inherent properties of RRNS.

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction-double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called 'HCG' for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.