Decimal multiplication using compact BCD multiplier

James, Rekha K.; Shahana, T. K.; Jacob, K. Poulose; Sasi, Sreela

doi:10.1109/iced.2008.4786744

Cited by 26 publications

(15 citation statements)

References 13 publications

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“…al [16] partition the two decimal operands (e.g., X = x 8 x 4 x 2 x 1 and Y = y 8 y 4 y 2 y 1 ), to their most significant bits (i.e., x 8 and y 8 ), and the remaining three bits (i.e., x 4 x 2 x 1 and y 4 y 2 y 1 ). Three products, one BCD and two binary, are computed in parallel.…”

Section: Decimal Operand Partitioning Approachmentioning

confidence: 99%

“…One of the two binary products (i.e., R versus S or T ) is selected and converted to BCD which is further multiplexed along Q, thus leading to the final BCD product. Figure 2, reproduced from [16], depicts the required building blocks, where the critical delay path is marked, and the gate-level evaluation leads to overall delay of 19 G.…”

Section: Decimal Operand Partitioning Approachmentioning

confidence: 99%

“…Fig. 1 Two 4 × 4 BCD array multiplier architectures [11] The specific short word binary product to 2-digit BCD converter was originally offered in [14], later in [4,16,28], and recently in [1]. However, the original design [14] is believed to be erroneous as noted in [4], where a corrected, but not very efficient design is presented.…”

Section: Introductionmentioning

confidence: 99%

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Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Gorgin

Jaberipur

Asl

2014

Circuits Syst Signal Process

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Partial product generation (PPG), in radix-10 multiplication hardware, is often done through selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA realization of classical PPG via digit-by-digit multiplication has recently attracted some researchers. For example, a sequential multiplier, squarer, divider, FPGA parallel multiplier, and array multiplier are all based on a specific binary-coded decimal (BCD) digit multiplier (BDM). Most BDMs, as we have encountered, compute the binary product of two 1-digit BCD operands, and convert it to 2-digit BCD product. We provide our own version of two of these works with some adjustments and improvements, and offer two new low-cost BDMs in this category. However, a recent FPGA BDM uses straightforward truth table approach from scratch and skips binary product generation. We redesign the latter via low-level FPGA programming, and also provide its ASIC realization. We synthesize all the studied and new designs on ASIC and FPGA platforms, exhaustively check them for correctness, and compare their performance, to show that our two new designs, and the ASIC and new FPGA realizations of the aforementioned fully truth table-based design, outperform the previous ones in terms of one or more figures of merit.

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Section: Decimal Operand Partitioning Approachmentioning

confidence: 99%

Section: Decimal Operand Partitioning Approachmentioning

confidence: 99%

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Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Gorgin

Jaberipur

Asl

2014

Circuits Syst Signal Process

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“…In the conversion of such an irregular fraction into recurring decimal, ekadhika (by one more than the previous) process can be used. Assume a = 5; thus, we want to calculate the value of 1 59 . Hence, ekadhika purva (one more than the previous) is 5 + 1 = 6.…”

Section: Examplesmentioning

confidence: 99%

“…Thereby, hardware implementation of Applying Speci c Integrated Circuits (ASICs) has gained popularity during the last decade [1][2][3][4][5]. Generally, hardware implementation of the computer arithmetic circuits is based on binary number systems due to simplicity of operations from decimal number systems [6].…”

Section: Introductionmentioning

confidence: 99%

A new algorithm for the computation of the decimals of the inverse

Saha

Kumar

2017

Scientia Iranica

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Abstract. Ancient mathematical formulae can be directly applied to the optimization of the algebraic computation. A new algorithm used to compute decimals of the inverse based on such ancient mathematics is reported in this paper. Sahayaks (auxiliary fraction) sutra has been used for the hardware implementation of the decimals of the inverse. On account of the ancient formulae, reciprocal approximation of numbers can generate \on the y" either the rst exact n decimal of inverse, n being either arbitrary large or at least 6 in almost all cases. The reported algorithm has been implemented, and functionality has been checked in T-Spice. Performance parameters, like propagation delay and dynamic switching power consumptions, are calculated through spice-spectre of 90 nm CMOS technology. The propagation delay of the resulting 4-digit reciprocal approximation algorithm was only 1:8 uS and consumed 24:7 mW power. The implementation methodology o ered substantial reduction of propagation delay and dynamic switching power consumption from its counterpart (NR) based implementation.

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