Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Abstract

Partial product generation (PPG), in radix-10 multiplication hardware, is often done through selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA realization of classical PPG via digit-by-digit multiplication has recently attracted some researchers. For example, a sequential multiplier, squarer, divider, FPGA parallel multiplier, and array multiplier are all based on a specific binary-coded decimal (BCD) digit multiplier (BDM). Most BDMs, as we have encountered, compute the binary product of two 1-digit BCD operands, and convert it to 2-digit BCD product. We provide our own version of two of these works with some adjustments and improvements, and offer two new low-cost BDMs in this category. However, a recent FPGA BDM uses straightforward truth table approach from scratch and skips binary product generation. We redesign the latter via low-level FPGA programming, and also provide its ASIC realization. We synthesize all the studied and new designs on ASIC and FPGA platforms, exhaustively check them for correctness, and compare their performance, to show that our two new designs, and the ASIC and new FPGA realizations of the aforementioned fully truth table-based design, outperform the previous ones in terms of one or more figures of merit.

High-speed binary coded decimal digit multipliers with multiple error detection

“…Many of the previous designs and methods are based on different BCD-based coding techniques [7][8][9] or utilizing optimal adder structures for partial product generation and reduction [10][11][12][13][14][15] to reduce area, delay or power consumption. Some designs utilize the methods for improving the implementation of BCD multipliers on FPGAs [16][17][18]. In addition, there exist a variety of methods to obtain efficient binary to decimal converters useful for the BCD multiplication such as [11,[19][20][21].…”

High-speed radix-10 multiplication using partial shifter adder tree-based convertor

“…signed digit radix-10 BCD multiplication using a multi-operand adder structure [6] offers improvements in performance in comparison with conventional BCD multiplier. Available binary-to-BCD converter uses for BCD digits multiplier (BDM) in [7], Gorgin's [7] multiplier design was based on the truth table for conversion of binary number into BCD digits and develops a new combinational design architecture for implementation on FPGA. Vazquez [8] designs a high-speed decimal multiplier using three stage parallel process.…”