Design of High Speed Vedic Multiplier for Decimal Number System

Saha, Prabir; Banerjee, Arindam; Dandapat, Anup; Bhattacharyya, P.

doi:10.1007/978-3-642-31494-0_10

Cited by 7 publications

(3 citation statements)

References 16 publications

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“…Moreover, the application of the Vedic algorithm reduces the amount of the hardware, owing to the reduction of propagation delay and dynamic switching power consumptions. Optimized BCD 4221 [19] coding techniques have been incorporated in this design to reduce the propagation delay. The performance parameters like propagation delay and dynamic switching power consumption is shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Integer division technique for signal processing applications

Kumar

Sharma

Saha

2015

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication

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Algorithmic implementation of integer division technique based on ancient Vedic mathematics is reported in this paper. The potentiality of the 'Nikhilam Navatascaramam Dasatah (NND)' (all from 9 and last from 10)' sutra of Vedic mathematics was adopted to implement the high speed integer division. Optimized 4221 BCD encoding technique was incorporated with Vedic mathematics, to implement such divider for practical signal processing applications. Propagation delay and dynamic switching power consumption of division circuitry were minimized significantly through stage reduction techniques of such sutra (formulae). The functionality of the division circuitry was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx tool (VHDL language). The propagation delay of the resulting 6÷3 digit divisor circuitry was only ~41ns and consumed ~93mW power. Amalgam-nation of BCD arithmetic with ancient Vedic mathematics, substantial amount of iterations were eliminated owing to ~20% reduction in delay and ~12% reduction in power from its counterpart.

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Section: Resultsmentioning

confidence: 99%

Integer division technique for signal processing applications

Kumar

Sharma

Saha

2015

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication

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“…Final result have been computed through Multiply and Accumulate (MAC) unit to produce the convolution sum. BCD arithmetic [17] has been incorporated to implement the practical VLSI implementation of the convolved chip. The proposed architecture does not impose any limitation on calculation for convolution sum, as long as the chosen method does not introduce round-off errors.…”

Section: Introductionmentioning

confidence: 99%

Implementation of high speed processor for computing convolution sum for DSP applications

Saha

Kumar

Sharma

2015

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication

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In this paper, we report on transistor level (ASIC) implementation of high speed processor for the first time, for computing convolution sum (linear and circular) of two sequences. The convolution sum was calculated through the orientation of the sequences into array formation for parallel processing, owing towards high speed architecture design. The architectures were implemented and functionality was verified through spice simulator. The mathematical transformation along with binary coded decimal(BCD) arithmetic have been incorporated for the practical implementation of convolution sum, ensure substantial reduction of propagation delay in comparison with earlier reported architectures. The performance parameters such as propagation delay, dynamic switching power consumption were calculated through spice using 90nm CMOS technology. The propagation delay of the resulting 4-point linear convolution was only ~12.79ns and consumes ~27.56mW power with a layout area of ~9.06mm 2 . Moreover, performance parameters of 4-point circular convolution were ~14.8ns propagation delay with ~37.8mW switching power consumption.

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“…Several attempts by researchers are being reported in literature in designing the multipliers [1], [2]. To avoid the limitations and to reduce the computational complexity, some researchers attempt to design them using ancient Indian mathematics [3], [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

The Design of Reversible Multiplier Using Ancient Indian Mathematics

Banerjee

Das

2013

2013 International Symposium on Electronic System Design

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The main aim of this paper is to design binary as well as decimal reversible multiplier using the well known Nikhilam formula of ancient Indian mathematics. Reversible logic is an important alternate to reduce the power. However its design demands some additional inputs and garbage outputs. Our design offers less number of ancillary inputs and garbage outputs in comparison to the earlier similar work.

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Design of High Speed Vedic Multiplier for Decimal Number System

Cited by 7 publications

References 16 publications

Integer division technique for signal processing applications

Integer division technique for signal processing applications

Implementation of high speed processor for computing convolution sum for DSP applications

The Design of Reversible Multiplier Using Ancient Indian Mathematics

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