Automated synthesis of delay-reduced Reed-Muller universal logic module networks

Abstract

This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables.

Optimal design of combinational logic circuits using genetic algorithm and Reed-Muller Universal Logic Modules

“…Example8:F(a,b,c,d)= ( 0, 4,6,7,8,12,14,15 Fig. 14 it is clear that 100% fit circuit was evolved with lesser number of generations in method I in all the cases, but the optimal output is with the third method.…”

“…Ease of complementing and testing is an added advantage of this representation. Lot of work has been done in this area regarding design and minimization techniques for RM logic, and conversion between RM and Boolean functions [6], [7].Implementation of RM functions can be made using discrete components or Reed Muller Universal Logic Modules (RM ULMs). Here single control line RM-ULM has been used for implementing a logic function given in positive polarity Reed-Muller (PPRM) form.…”

“…A logic function with n-variables can be realized using 2 n -1 RM-ULM (1) s with n levels by standard implementation. Any implementation using less than 2 n -1 number of modules and / or lesser number of levels can be considered as an improvement in cost and or speed [6]. (1) is a device with 1-control input, 2 data inputs and a single output F. Its behavior is described as…”

“…In [5] A.H.Aguirre made an attempt to design combinational digital circuits using 2-1 multiplexers with Genetic programming. In [8], authors proposed the design of combinational logic circuits with 2 to 1 multiplexers using GA. Two different algorithms have been proposed in [6] using RM ULM, but it was not based on evolutionary techniques. They also have tested Boolean functions only up to 4 variables.…”