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We experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6×2 mm2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance

We report an 8 × 8 silicon photonic integrated Arrayed Waveguide Grating Router (AWGR) targeted for WDM routing applications in O-band. The AWGR was designed for cyclic-frequency operation with a channel spacing of 10 nm. The fabricated AWGR exhibits a compact footprint of 700 × 270 μm. Static device characterization revealed 3.545 dB maximum channel loss non-uniformity with 2.5 dB best-case channel insertion losses and 11 dB channel crosstalk, in good agreement with the simulated results. Successful data routing operation is demonstrated with 25 Gb/s signals for all 8 × 8 AWGR port combinations with a maximum power penalty of 2.45 dB.

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4×50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of −9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers.

Real‐time control of multiple cascaded devices is a key requirement for the development of complex silicon photonic circuits performing new sophisticated optical functionalities. This article describes how the dithering technique can be leveraged in combination with non‐invasive light probes to independently control the working point of many photonic components. The standard technique is extended by introducing the concept of orthogonal dithering signals to simultaneously discriminate the effect of different actuators, while the idea of frequency re‐use is discussed to limit the complexity of control systems in cascaded architectures. After a careful analysis of the problem, the article presents an automated feedback strategy to tune and lock photonic devices in the maxima/minima of their transfer functions with given response speed and sensitivity. The trade‐offs of this approach are discussed in detail to provide guidelines for the design of the feedback loop. Experimental demonstrations on a mesh of Mach‐Zehnder interferometers and on cascaded ring resonators are discussed to validate the proposed control architecture in different scenarios and applications.

A silicon photonic circuit comprising all the building blocks necessary to demonstrate optical communication between two sockets interconnected through an Arrayed Waveguide Grating Router is reported. The paper focuses on the robustness of the interconnection scheme to the unavoidable wavelength and thermal fluctuations observed in real datacenter environments. To improve the reliability of the system, a feedback control mechanism, based on ContactLess Integrated Photonic Probes and heater actuators, is added to the interconnection to monitor in parallel the working point of each sensitive device and keep it locked in real-time. Experimental results demonstrate successful operations in a 30 Gbit/s data routing scenario at 5 • 10 −11 bit error rate, irrespective of sudden wavelength shifts of up to 200 pm or of iterated thermal variations in a 10°C temperature range, with a recovery time of around 30 ms. These results prove that AWGR-based interconnections equipped with real-time drift compensation systems can be a viable option in multi-socket layouts even in highly demanding environments. Index Terms-Silicon photonics, thermal drift compensation, CLIPP sensor, wavelength division multiplexing, AWGR-based interconnect I. INTRODUCTIONWith the demand for data traffic capacity in intra datacenter applications roughly doubling every year [1], novel techniques must be developed to cope with traffic growth. Two key problems that arise when scaling up capacity are the increased power consumption of the processors and the latency in the communication between them. These problems have driven research interest on novel multi-socket-boards (MSB), that integrate several processor sockets on a single board interconnected with a low latency interface. Schemes as Intel's QPI [2] can offer glue-less interconnection but are limited to

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Electronic Content Addressable Memories (CAM) implement Address Look-Up (AL) table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI)-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM) is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR) gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM) cell and a 4-bit Matchline (ML) configuration, supporting a third state of the "logical X" value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM) sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM) memory access requests.