Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

Vagionas, Christos; Maniotis, Pavlos; Pitris, Stelios; Miliou, Amalia; Pleros, Nikos

doi:10.3390/app7070700

Cited by 16 publications

(11 citation statements)

References 54 publications

(114 reference statements)

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“…In this section we present our most recent results [54][55][56][57][58][59] extending the previous single cells demonstrations towards the first 2-bit all-optical ML architecture, with matching or not matching information of the result of the content-based search operation in its two CAM cells being wavelength-encoded and optically multiplexed by an AWG multiplexer. The final output and matching signal is then regenerated at a cascaded SOA-based XGM WC, which collects the multi-wavelength ML signals.…”

Section: Optical Cams and ML Architectures For Fast Al Tablesmentioning

confidence: 77%

“…Within this frame, our most recent research efforts have been aligned towards overcoming the frequency barrier set by electronic memories by realizing CAM-and RAM-based configurations completely in the optical domain [25][26][27][54][55][56][57][58][59]. The first all-optical B-CAM cell demonstrations was recently reported based on a monolithically integrated SOA-MZI-based FF with speed capabilities of up to 10 Gb s −1 [56] achieving a large leap in the speed of memory content addressing operations; it was later followed by a series of significant achievements [54][55][56][57][58][59] also advancing the scalability [57] and architectural complexity by introducing all-optical T-CAM cell configurations [55] and realizing optical CAM ML [59] architectures. While optical CAM cells have reached 10 Gb s −1 operation, optical RAM cells have been limited to speeds less than 5 GHz [56].…”

Section: Architecture Of An Optical Al Tablementioning

confidence: 99%

“…This configuration was later expanded into a completely optical T-CAM cell architecture extending the capabilities of the experimentally demonstrated 10 Gb s −1 optical B-CAM cell to the third matching state 'X' or 'care/don't care', enabling in this way the subnet-masked operation required in modern router applications [57]. The scaling credentials of the proposed scheme were successfully evaluated through physical layer simulations in the VPIphotonics Design Suite [65] at 10 Gb s −1 [54]. Recently, the first all-optical T-CAM cell was experimentally validated at 10 Gb s −1 ; it comprised of two monolithically integrated InP FF and a SOA-MZI optical XOR gate.…”

Section: Optical Cams and ML Architectures For Fast Al Tablesmentioning

confidence: 99%

“…Discussing the scaling from single-bit to multi-bit architectures and fully describing the vision of light-based AL functionalities, we also present our latest experimental work on a 2-bit optical CAM ML architecture for AL at 10 Gb s −1 , the fast-performing 2-bit search operation based on content-based addressing of its stored data. The performance evaluation of the 2-bit ML is then extended with a physical layer investigation of a 4-bit all-optical CAM row architecture with ternary storing capabilities per cell to support the wildcard bit operation as well WDM-multiplexing of its four memory outputs for fast parallel comparison of the row, aiming to highlight the potential for speeds even up to 20 Gb s −1 , in the case of fully integrated architectures [54]. Finally, we discuss the progress witnessed in the optical CAM and RAM areas and present a comparative study against electronic counterparts, so as to reveal the potential future challenges and next steps towards optical AL routing table architectures.…”

Section: Introductionmentioning

confidence: 99%

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Optical memory architectures for fast routing address look-up (AL) table operation

et al. 2019

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Today, the increasing demand for fast routing processes has turned the address look-up (AL) operation into one of the main critical performance operations in modern optical networks, since it conventionally relies on slow-performing AL tables. Specifically, AL memory tables are comprised of content addressable memories (CAMs) for storing a known route of the forwarding information base of the router, and random access memories (RAMs) for storing the respective output port for this route. They thus allow for a one-cycle search operation of a packet's destination address, yet they typically operate at speeds well below 1 GHz, in contrast with the vastly increasing optical line rates. In this paper, we present our overall vision towards light-based optical AL memory functionalities that may facilitate faster router AL operations, as the means to replace slow-performing electronic counterparts. In order to achieve this, we report on the development of a novel optical RAM cell architecture that performs for the first time with a speed of up to 10 Gb s −1 , as well as our latest works on multi-bit 10 Gb s −1 optical CAM cell architectures. Specifically, the proposed optical RAM cell exploits a semiconductor optical amplifier-Mach-Zehnder interferometer in a push-pull configuration and deep saturation regime, doubling the speed of prior optical RAM cell configurations. Errorfree write/read operation is demonstrated with a peak power penalty of 6.2 dB and 0.4 dB, respectively. Next, we present the recent progress on optical CAM cell architectures, starting with an experimental demonstration of a 2-bit optical CAM match-line architecture that achieves an exact bitwise search operation of an incoming 2-bit destination address at 10 Gb s −1 , while the analysis is also extended to a numerical evaluation of a multi-cell 4-bit CAM-based row architecture with wavelength division multiplexed outputs for fast parallel memory operations at speeds of up to 4×20 Gb s −1 . Finally, we present a comparative study between electronic and optical RAMs and CAMs in terms of energy and speed and discuss the further challenges towards our vision. entries, even causing the depletion of the remaining IPv4 address space and leading to the advent of an IPv6 protocol with a quadrupled need for address look-up (AL) requirements [5]. This increasing need for faster routing functionalities, including AL, which also requires fast hardware memories to perform fast look-up of the packet's destination address immediately upon its arrival and across the forwarding information base (FIB) of the router.On the path to speeding up hardware memory and lower latency times when fetching data, state-of-the-art highly performing electronic static random access memory (RAM) cell technology has managed to achieve operation up to 5 GHz [6][7][8]. However, RAMs are inherently limited in fast AL as, owing to the address-based fetching of data, they would require multiple sequential random access to the memory and consecutive searches of the desired content. As a re...

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Section: Optical Cams and ML Architectures For Fast Al Tablesmentioning

confidence: 77%

Section: Architecture Of An Optical Al Tablementioning

confidence: 99%

Section: Optical Cams and ML Architectures For Fast Al Tablesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optical memory architectures for fast routing address look-up (AL) table operation

et al. 2019

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“…The priority trie [17] for IP address lookup [18] removes any empty internal nodes in a trie. The priority trie is constructed by repeatedly relocating the longest prefix included in the sub-trie of an empty node into that empty node.…”

Section: Priority Triementioning

confidence: 99%

A New Bloom Filter Architecture for FIB Lookup in Named Data Networking

Byun

Lim

2019

Applied Sciences

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Network traffic has increased rapidly in recent years, mainly associated with the massive growth of various applications on mobile devices. Named data networking (NDN) technology has been proposed as a future Internet architecture for effectively handling this ever-increasing network traffic. In order to realize the NDN, high-speed lookup algorithms for a forwarding information base (FIB) are crucial. This paper proposes a level-priority trie (LPT) and a 2-phase Bloom filter architecture implementing the LPT. The proposed Bloom filters are sufficiently small to be implemented with on-chip memories (less than 3 MB) for FIB tables with up to 100,000 name prefixes. Hence, the proposed structure enables high-speed FIB lookup. The performance evaluation result shows that FIB lookups for more than 99.99% of inputs are achieved without needing to access the database stored in an off-chip memory.

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