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Departing from traditional server-centric data center architectures towards disaggregated systems that can offer increased resource utilization at reduced cost and energy envelopes, the use of high-port switching with highly stringent latency and bandwidth requirements becomes a necessity. We present an optical switch architecture exploiting a hybrid broadcast-and-select/wavelength routing scheme with small-scale optical feedforward buffering. The architecture is experimentally demonstrated at 10Gb/s, reporting error-free performance with a power penalty of <2.5dB. Moreover, network simulations for a 256-node system, revealed low-latency values of only 605nsec, at throughput values reaching 80% when employing 2-packet-size optical buffers, while multi-rack network performance was also investigated.

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4×50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of −9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers.

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Real‐time control of multiple cascaded devices is a key requirement for the development of complex silicon photonic circuits performing new sophisticated optical functionalities. This article describes how the dithering technique can be leveraged in combination with non‐invasive light probes to independently control the working point of many photonic components. The standard technique is extended by introducing the concept of orthogonal dithering signals to simultaneously discriminate the effect of different actuators, while the idea of frequency re‐use is discussed to limit the complexity of control systems in cascaded architectures. After a careful analysis of the problem, the article presents an automated feedback strategy to tune and lock photonic devices in the maxima/minima of their transfer functions with given response speed and sensitivity. The trade‐offs of this approach are discussed in detail to provide guidelines for the design of the feedback loop. Experimental demonstrations on a mesh of Mach‐Zehnder interferometers and on cascaded ring resonators are discussed to validate the proposed control architecture in different scenarios and applications.

A silicon photonic circuit comprising all the building blocks necessary to demonstrate optical communication between two sockets interconnected through an Arrayed Waveguide Grating Router is reported. The paper focuses on the robustness of the interconnection scheme to the unavoidable wavelength and thermal fluctuations observed in real datacenter environments. To improve the reliability of the system, a feedback control mechanism, based on ContactLess Integrated Photonic Probes and heater actuators, is added to the interconnection to monitor in parallel the working point of each sensitive device and keep it locked in real-time. Experimental results demonstrate successful operations in a 30 Gbit/s data routing scenario at 5 • 10 −11 bit error rate, irrespective of sudden wavelength shifts of up to 200 pm or of iterated thermal variations in a 10°C temperature range, with a recovery time of around 30 ms. These results prove that AWGR-based interconnections equipped with real-time drift compensation systems can be a viable option in multi-socket layouts even in highly demanding environments. Index Terms-Silicon photonics, thermal drift compensation, CLIPP sensor, wavelength division multiplexing, AWGR-based interconnect I. INTRODUCTIONWith the demand for data traffic capacity in intra datacenter applications roughly doubling every year [1], novel techniques must be developed to cope with traffic growth. Two key problems that arise when scaling up capacity are the increased power consumption of the processors and the latency in the communication between them. These problems have driven research interest on novel multi-socket-boards (MSB), that integrate several processor sockets on a single board interconnected with a low latency interface. Schemes as Intel's QPI [2] can offer glue-less interconnection but are limited to

The explosive growth of deep learning applications has triggered a new era in computing hardware, targeting the efficient deployment of multiply-and-accumulate operations. In this realm, integrated photonics have come to the foreground as a promising energy efficient deep learning technology platform for enabling ultra-high compute rates. However, despite integrated photonic neural network layouts have already penetrated successfully the deep learning era, their compute rate and noise-related characteristics are still far beyond their promise for high-speed photonic engines. Herein, we demonstrate experimentally a noise-resilient deep learning coherent photonic neural network layout that operates at 10GMAC/sec/axon compute rates and follows a noise-resilient training model. The coherent photonic neural network has been fabricated as a silicon photonic chip and its MNIST classification performance was experimentally evaluated to support accuracy values of >99% and >98% at 5 and 10GMAC/sec/axon, respectively, offering 6× higher on-chip compute rates and >7% accuracy improvement over state-of-the-art coherent implementations.