We fabricated the HfZrO 2 (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 5 program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 4 s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W eff per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (>10 8), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices. INDEX TERMS Gate all around, junctionless, nanosheet, multi gate, stacked FET.

Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-induced barrier lowering value of 4.47 mV/V and immunity to gate-induced drain leakage. Finally, a technology computer-aided design simulation was conducted to verify the experimental results.

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This study reports the ferroelectric (FE) layer of Hf0.5Zr0.5O2 (HZO) film on a Ge gate-all-around field-effect-transistor (GAAFET) with inversion mode (IM) and junctionless (JL) mode, and is the first that discuss the association of the JL field-effect transistor conduction mechanism in the subthreshold region with the transient negative capacitance (TNC) effect of the FE layer are discussed. The IM Ge FE-GAAFET exhibited a minimum subthreshold slope (SSmin) of 55 mV dec−1 and a high ION/IOFF ratio of >106. The sub-60 mV dec−1 SS result demonstrates surface potential amplification, which is attributed to the TNC effect. Furthermore, the Ge JL FE-GAAFETs exhibited an SSmin of 58 mV dec−1, a high ION/IOFF ratio (>105), and reverse drain-induced barrier lowering when compared with baseline HfO2 devices. These IM and JL Ge FE-GAAFETs are highly suitable for low-power integrated circuit applications.